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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
[all …]
H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 vcm-supply:
42 vcc-drv-supply:
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H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
38 vcm-supply:
40 Common-mode voltage regulator.
[all …]
/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-frequency-admv10131 What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-altvoltage1_i_calibphase
3 Contact: linux-iio@vger.kernel.org
5 Read/write unscaled value for the Local Oscillatior path quadrature I phase shift.
7 What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-altvoltage1_q_calibphase
9 Contact: linux-iio@vger.kernel.org
11 Read/write unscaled value for the Local Oscillatior path quadrature Q phase shift.
15 Contact: linux-iio@vger.kernel.org
17 Read/write value for the Local Oscillatior Feedthrough Offset Calibration I Positive
22 Contact: linux-iio@vger.kernel.org
24 Read/write value for the Local Oscillatior Feedthrough Offset Calibration Q Positive side.
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_mode.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 POS = 0, /* positive */
32 /* Clock Phase. This clock phase only applies to Panel. */
/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dsemtech,sx9324.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gwendal Grignou <gwendal@chromium.org>
11 - Daniel Campello <campello@chromium.org>
17 - $ref: /schemas/iio/iio.yaml#
32 vdd-supply:
35 svdd-supply:
38 "#io-channel-cells":
41 semtech,ph0-pin:
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/linux/include/uapi/linux/media/raspberrypi/
H A Dpisp_be_config.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
5 * Copyright (C) 2021 - Raspberry Pi Ltd
98 * struct pisp_be_global_config - PiSP global enable bitmaps
112 * struct pisp_be_input_buffer_config - PiSP Back End input buffer
121 * struct pisp_be_dpc_config - PiS
[all...]
/linux/Documentation/devicetree/bindings/bus/
H A Dmoxtet.txt4 - compatible : Should be "cznic,moxtet"
5 - #address-cells : Has to be 1
6 - #size-cells : Has to be 0
7 - spi-cpol : Required inverted clock polarity
8 - spi-cpha : Required shifted clock phase
9 - interrupts : Must contain reference to the shared interrupt line
10 - interrupt-controller : Required
11 - #interrupt-cells : Has to be 1
14 ../spi/spi-bus.txt.
17 - reg : Should be position on the Moxtet bus (how many Moxtet
[all …]
/linux/drivers/parport/
H A Dieee1284.c2 * IEEE-1284 implementation for parport.
5 * Carsten Gross <carsten@sol.wohnheim.uni-ulm.de>
10 * read/write requests to low-level drivers.
38 up (&port->physport->ieee1284.irq); in parport_ieee1284_wakeup()
49 * parport_wait_event - wait for an event on a parallel port
68 if (!port->physport->cad->timeout) in parport_wait_event()
73 timer_setup(&port->timer, timeout_waiting_on_port, 0); in parport_wait_event()
74 mod_timer(&port->timer, jiffies + timeout); in parport_wait_event()
75 ret = down_interruptible (&port->physport->ieee1284.irq); in parport_wait_event()
76 if (!timer_delete_sync(&port->timer) && !ret) in parport_wait_event()
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/linux/drivers/char/
H A Dppdev.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * This is the code behind /dev/parport* -- it allows a user-space
8 * Copyright (C) 1998-2000, 2002 Tim Waugh <tim@cyberelk.net>
20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
21 * confused with ioctl(fd, SETPHASER, &stun). ;-)
37 * GETPHASE gets the current IEEE1284 phase
38 * GETFLAGS gets current (user-visible) flags
39 * SETFLAGS sets current (user-visible) flags
47 * - On error, copy_from_user and copy_to_user do not return -EFAULT,
48 * They return the positive number of bytes *not* copied due to address
[all …]
/linux/Documentation/input/devices/
H A Datarikbd.rst12 provides a convenient connection point for a mouse and switch-type joysticks.
13 The ikbd processor also maintains a time-of-day clock with one second
18 The ikbd communicates with the main processor over a high speed bi-directional
41 0xF8-0xFB relative mouse position records (lsbs determined by
43 0xFC time-of-day
56 approximately 200 counts (phase changes or 'clicks') per inch of travel. The
67 ---------------------------
92 +127...-128 range, the motion is broken into multiple packets.
97 ---------------------------
104 ---------------------
[all …]
H A Diforce-protocol.rst7 Home page at `<http://web.archive.org/web/*/http://www.esil.univ-mrs.fr>`_
16 specify force effects to I-Force 2.0 devices. None of this information comes
25 send data to your I-Force device based on what you read in this document.
30 All values are hexadecimal with big-endian encoding (msb on the left). Beware,
31 values inside packets are encoded using little-endian. Bytes whose roles are
35 ------------------------
64 00 X-Axis lsb
65 01 X-Axis msb
66 02 Y-Axis lsb, or gas pedal for a wheel
67 03 Y-Axis msb, or brake pedal for a wheel
[all …]
/linux/Documentation/i2c/
H A Dfault-codes.rst10 ----------------------------------
14 some cases, such as re-initializing (and maybe resetting). After such
27 -------------------------
29 some positive number indicating a non-fault return. The specific
31 though most Linux systems use <asm-generic/errno*.h> numbering.
93 Returned by I2C adapters to indicate that the address phase
119 or SMBus (or chip-specific) protocol specifications. One
121 (from the SMBus slave) is outside the range 1-32 bytes.
/linux/Documentation/scsi/
H A DChangeLog.sym53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version sym53c8xx-1.7.3c
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Backport from SYM-2 the work-around that allows to support
7 - Check that we received at least 8 bytes of INQUIRY response
9 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
10 - + A couple of minor changes.
12 Sat Apr 7 19:30 2001 Gerard Roudier (groudier@club-internet.fr)
13 * version sym53c8xx-1.7.3b
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/linux/sound/pci/cs46xx/
H A Dcs46xx_dsp_scb_types.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
32 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0]
35 |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1|
44 u32 npaw; /* Next-Page Address Word */
48 31-30 29 28 [27:16] [15:12] [11:3] [2:0]
50 |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | |
51 |page|__|__| ___________________________|_________|__page, if !sample-end___________|____|
53 u32 npcw; /* Next-Page Control Word */
54 u32 lbaw; /* Loop-Begin Address Word */
55 u32 nplbaw; /* Next-Page after Loop-Begin Address Word */
[all …]
/linux/sound/soc/
H A Dsoc-utils.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-util.c -- ALSA SoC Audio Layer utility functions
23 /* Positive, Zero values are not errors */ in snd_soc_ret()
29 case -EPROBE_DEFER: in snd_soc_ret()
30 case -ENOTSUPP: in snd_soc_ret()
31 case -EOPNOTSUPP: in snd_soc_ret()
84 * snd_soc_tdm_params_to_bclk - calculate bclk from params and tdm slot info.
87 * tdm slot width. Optionally round-up the slot count to a given multiple.
95 * I2S mode, which has a left and right phase so the number of slots is always
153 if (component->driver == &dummy_platform) in dummy_dma_open()
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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H A Dsmu13_driver_if_v13_0_0.h175 SVI_PSI_0, // Full phase count (default)
176 SVI_PSI_1, // Phase count 1st level
177 SVI_PSI_2, // Phase count 2nd level
178 SVI_PSI_3, // Single phase operation + active diode emulation
179 SVI_PSI_4, // Single phase operation + passive diode emulation *optional*
182 SVI_PSI_7, // Automated phase shedding and diode emulation
503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
1007 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1008 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
[all …]
H A Dsmu13_driver_if_v13_0_7.h176 SVI_PSI_0, // Full phase count (default)
177 SVI_PSI_1, // Phase count 1st level
178 SVI_PSI_2, // Phase count 2nd level
179 SVI_PSI_3, // Single phase operation + active diode emulation
180 SVI_PSI_4, // Single phase operation + passive diode emulation *optional*
183 SVI_PSI_7, // Automated phase shedding and diode emulation
504 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
507 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
1016 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1017 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
[all …]
H A Dsmu14_driver_if_v14_0.h184 SVI_PSI_0, // Full phase count (default)
185 SVI_PSI_1, // Phase count 1st level
186 SVI_PSI_2, // Phase count 2nd level
187 SVI_PSI_3, // Single phase operation + active diode emulation
188 SVI_PSI_4, // Single phase operation + passive diode emulation *optional*
191 SVI_PSI_7, // Automated phase shedding and diode emulation
517 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
520 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
1106 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1107 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_sp.h3 * Copyright 2011-2013 Broadcom Corporation
10 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
45 * re-try to submit this one. This flag can be set only in sleepable
101 /************************* VLAN-MAC commands related parameters ***************/
178 /* Return positive if entry was optimized, 0 - if not, negative
211 * Must run under exe_queue->lock
227 * Must run under exe_queue->lock
242 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
250 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
322 * will be copied. Note elements are 4-byte aligned
[all …]
/linux/drivers/spi/
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
25 #define CDNS_SPI_NAME "cdns-spi"
48 #define CDNS_SPI_CR_CPHA 0x00000004 /* Clock Phase Control */
63 * SPI Configuration Register - Baud rate and target select
102 * struct cdns_spi - This definition defines spi driver instance
136 return readl_relaxed(xspi->regs + offset); in cdns_spi_read()
141 writel_relaxed(val, xspi->regs + offset); in cdns_spi_write()
145 * cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
[all …]
/linux/include/uapi/linux/
H A Dinput.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (c) 1999-2002 Vojtech Pavlik
20 #include "input-event-codes.h"
56 * IOCTLs (0x00 - 0x7f)
67 * struct input_absinfo - use
411 __u16 phase; global() member
[all...]
/linux/Documentation/RCU/Design/Memory-Ordering/
H A DTree-RCU-Memory-Ordering.rst2 A Tour Through TREE_RCU's Grace-Period Memory Ordering
13 grace-period memory ordering guarantee is provided.
18 RCU grace periods provide extremely strong memory-ordering guarantees
19 for non-idle non-offline code.
22 period that are within RCU read-side critical sections.
25 of that grace period that are within RCU read-side critical sections.
27 Note well that RCU-sched read-side critical sections include any region
30 an extremely small region of preemption-disabled code, one can think of
36 In the most common use case, phase one removes an element from
37 a linked RCU-protected data structure, and phase two frees that element.
[all …]
/linux/drivers/media/rc/
H A Drc-ir-raw.c1 // SPDX-License-Identifier: GPL-2.0
2 // rc-ir-raw.c - handle IR pulse/space events
11 #include "rc-core-priv.h"
26 struct rc_dev *dev = raw->dev; in ir_raw_event_thread()
30 while (kfifo_out(&raw->kfifo, &ev, 1)) { in ir_raw_event_thread()
33 dev_warn_once(&dev->dev, "nonsensical timing event of duration 0"); in ir_raw_event_thread()
34 if (is_timing_event(raw->prev_ev) && in ir_raw_event_thread()
35 !is_transition(&ev, &raw->prev_ev)) in ir_raw_event_thread()
36 dev_warn_once(&dev->dev, "two consecutive events of type %s", in ir_raw_event_thread()
40 if (dev->enabled_protocols & in ir_raw_event_thread()
[all …]

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