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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
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H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 vcm-supply:
42 vcc-drv-supply:
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H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
38 vcm-supply:
40 Common-mode voltage regulator.
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-frequency-admv10131 What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_i_calibphase
3 Contact: linux-iio@vger.kernel.org
5 Read/write unscaled value for the Local Oscillatior path quadrature I phase shift.
7 What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_q_calibphase
9 Contact: linux-iio@vger.kernel.org
11 Read/write unscaled value for the Local Oscillatior path quadrature Q phase shift.
15 Contact: linux-iio@vger.kernel.org
17 Read/write value for the Local Oscillatior Feedthrough Offset Calibration I Positive
22 Contact: linux-iio@vger.kernel.org
24 Read/write value for the Local Oscillatior Feedthrough Offset Calibration Q Positive side.
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H A Dsysfs-bus-counter3 Contact: linux-iio@vger.kernel.org
11 Contact: linux-iio@vger.kernel.org
13 Selects the external clock pin for phase counting mode of
16 MTCLKA-MTCLKB:
18 phase clock.
20 MTCLKC-MTCLKD:
22 phase clock.
26 Contact: linux-iio@vger.kernel.org
33 Contact: linux-iio@vger.kernel.org
39 Contact: linux-iio@vger.kernel.org
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/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32-bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max
16 - Pulse input 3 lines
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/linux/drivers/staging/sm750fb/
H A Dddk750_mode.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 POS = 0, /* positive */
32 /* Clock Phase. This clock phase only applies to Panel. */
/linux/Documentation/driver-api/pm/
H A Ddevices.rst1 .. SPDX-License-Identifier: GPL-2.0
10 :Copyright: |copy| 2010-2011 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
18 management (PM) code is also driver-specific. Most drivers will do very
22 This writeup gives an overview of how drivers interact with system-wide
25 background for the domain-specific work you'd do with any specific driver.
31 Drivers will use one or both of these models to put devices into low-power
36 Drivers can enter low-power states as part of entering system-wide
37 low-power states like "suspend" (also known as "suspend-to-RAM"), or
39 "suspend-to-disk").
42 by implementing various role-specific suspend and resume methods to
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/linux/Documentation/devicetree/bindings/iio/proximity/
H A Dsemtech,sx9324.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gwendal Grignou <gwendal@chromium.org>
11 - Daniel Campello <campello@chromium.org>
17 - $ref: /schemas/iio/iio.yaml#
32 vdd-supply:
35 svdd-supply:
38 "#io-channel-cells":
41 semtech,ph0-pin:
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/linux/include/uapi/linux/media/raspberrypi/
H A Dpisp_be_config.h1 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
5 * Copyright (C) 2021 - Raspberry Pi Ltd
97 * struct pisp_be_global_config - PiSP global enable bitmaps
111 * struct pisp_be_input_buffer_config - PiSP Back End input buffer
120 * struct pisp_be_dpc_config - PiSP Back End DPC config
138 * struct pisp_be_geq_config - PiSP Back End GEQ config
150 #define PISP_BE_GEQ_SLOPE ((1 << 10) - 1)
158 * struct pisp_be_tdn_input_buffer_config - PiSP Back End TDN input buffer
167 * struct pisp_be_tdn_config - PiSP Back End TDN config
190 * struct pisp_be_tdn_output_buffer_config - PiSP Back End TDN output buffer
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/linux/Documentation/devicetree/bindings/bus/
H A Dmoxtet.txt4 - compatible : Should be "cznic,moxtet"
5 - #address-cells : Has to be 1
6 - #size-cells : Has to be 0
7 - spi-cpol : Required inverted clock polarity
8 - spi-cpha : Required shifted clock phase
9 - interrupts : Must contain reference to the shared interrupt line
10 - interrupt-controller : Required
11 - #interrupt-cells : Has to be 1
14 ../spi/spi-bus.txt.
17 - reg : Should be position on the Moxtet bus (how many Moxtet
[all …]
/linux/drivers/parport/
H A Dieee1284.c2 * IEEE-1284 implementation for parport.
5 * Carsten Gross <carsten@sol.wohnheim.uni-ulm.de>
10 * read/write requests to low-level drivers.
38 up (&port->physport->ieee1284.irq); in parport_ieee1284_wakeup()
49 * parport_wait_event - wait for an event on a parallel port
68 if (!port->physport->cad->timeout) in parport_wait_event()
73 timer_setup(&port->timer, timeout_waiting_on_port, 0); in parport_wait_event()
74 mod_timer(&port->timer, jiffies + timeout); in parport_wait_event()
75 ret = down_interruptible (&port->physport->ieee1284.irq); in parport_wait_event()
76 if (!del_timer_sync(&port->timer) && !ret) in parport_wait_event()
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/linux/drivers/char/
H A Dppdev.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * This is the code behind /dev/parport* -- it allows a user-space
8 * Copyright (C) 1998-2000, 2002 Tim Waugh <tim@cyberelk.net>
20 * SETPHASE set the IEEE 1284 phase of a particular mode. Not to be
21 * confused with ioctl(fd, SETPHASER, &stun). ;-)
37 * GETPHASE gets the current IEEE1284 phase
38 * GETFLAGS gets current (user-visible) flags
39 * SETFLAGS sets current (user-visible) flags
47 * - On error, copy_from_user and copy_to_user do not return -EFAULT,
48 * They return the positive number of bytes *not* copied due to address
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/linux/Documentation/input/devices/
H A Datarikbd.rst12 provides a convenient connection point for a mouse and switch-type joysticks.
13 The ikbd processor also maintains a time-of-day clock with one second
18 The ikbd communicates with the main processor over a high speed bi-directional
41 0xF8-0xFB relative mouse position records (lsbs determined by
43 0xFC time-of-day
56 approximately 200 counts (phase changes or 'clicks') per inch of travel. The
67 ---------------------------
92 +127...-128 range, the motion is broken into multiple packets.
97 ---------------------------
104 ---------------------
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H A Diforce-protocol.rst7 Home page at `<http://web.archive.org/web/*/http://www.esil.univ-mrs.fr>`_
16 specify force effects to I-Force 2.0 devices. None of this information comes
25 send data to your I-Force device based on what you read in this document.
30 All values are hexadecimal with big-endian encoding (msb on the left). Beware,
31 values inside packets are encoded using little-endian. Bytes whose roles are
35 ------------------------
64 00 X-Axis lsb
65 01 X-Axis msb
66 02 Y-Axis lsb, or gas pedal for a wheel
67 03 Y-Axis msb, or brake pedal for a wheel
[all …]
/linux/Documentation/driver-api/
H A Ddpll.rst1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
15 addition to plain PLL behavior incorporates a digital phase detector
82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
91 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as
104 1) Set on a pin - the configuration affects all dpll devices pin is
106 2) Set on a pin-dpll tuple - the configuration affects only selected
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/linux/Documentation/i2c/
H A Dfault-codes.rst10 ----------------------------------
14 some cases, such as re-initializing (and maybe resetting). After such
27 -------------------------
29 some positive number indicating a non-fault return. The specific
31 though most Linux systems use <asm-generic/errno*.h> numbering.
93 Returned by I2C adapters to indicate that the address phase
119 or SMBus (or chip-specific) protocol specifications. One
121 (from the SMBus slave) is outside the range 1-32 bytes.
/linux/include/linux/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
24 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
35 * POST_RATE_CHANGE - called after the clk rate change has successfully
44 * struct clk_notifier - associate a clk with a notifier
61 * struct clk_notifier_data - rate data to pass to the notifier callback
66 * For a pre-notifier, old_rate is the clk's rate before this rate
68 * post-notifier, old_rate and new_rate are both set to the clk's
78 * struct clk_bulk_data - Data used for bulk clk operations.
95 * clk_notifier_register - register a clock rate-change notifier callback
[all …]
/linux/Documentation/scsi/
H A DChangeLog.sym53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version sym53c8xx-1.7.3c
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Backport from SYM-2 the work-around that allows to support
7 - Check that we received at least 8 bytes of INQUIRY response
9 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
10 - + A couple of minor changes.
12 Sat Apr 7 19:30 2001 Gerard Roudier (groudier@club-internet.fr)
13 * version sym53c8xx-1.7.3b
[all …]
/linux/sound/pci/cs46xx/
H A Dcs46xx_dsp_scb_types.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
32 31 [30-28]27 [26:24] 23 22 21 20 [19:18] [17:16] 15 14 13 12 11 10 9 8 7 6 [5:0]
35 |H|_____ |H|_________|S_|D |__|__|______|_______|___|ne|__ |__ |__|__|_|_|_|_|_Count -1|
44 u32 npaw; /* Next-Page Address Word */
48 31-30 29 28 [27:16] [15:12] [11:3] [2:0]
50 |SV |LE|SE| Sample-end byte offset | | Page-map entry offset for next | |
51 |page|__|__| ___________________________|_________|__page, if !sample-end___________|____|
53 u32 npcw; /* Next-Page Control Word */
54 u32 lbaw; /* Loop-Begin Address Word */
55 u32 nplbaw; /* Next-Page after Loop-Begin Address Word */
[all …]
/linux/drivers/regulator/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
38 managed regulators and simple non-configurable regulators.
64 the netlink mechanism. User-space applications can subscribe to these events
65 for real-time updates on various regulator events.
75 They provide two I2C-controlled DC/DC step-down converters with
101 tristate "Active-semi act8865 voltage regulator"
106 This driver controls a active-semi act8865 voltage output
110 tristate "Active-semi ACT8945A voltage regulator"
113 This driver controls a active-semi ACT8945A voltage regulator
114 via I2C bus. The ACT8945A features three step-down DC/DC converters
[all …]
/linux/Documentation/power/
H A Dpci.rst13 power management refer to Documentation/driver-api/pm/devices.rst and
27 1.1. Native and Platform-Based Power Management
28 -----------------------------------------------
31 devices into states in which they draw less power (low-power states) at the
34 Usually, a device is put into a low-power state when it is underutilized or
36 again, it has to be put back into the "fully functional" state (full-power
41 PCI devices may be put into low-power states in two ways, by using the device
53 to put the device that sent it into the full-power state. However, the PCI Bus
68 Thus in many situations both the native and the platform-based power management
72 --------------------------------
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
[all …]
H A Dsmu13_driver_if_v13_0_0.h175 SVI_PSI_0, // Full phase count (default)
176 SVI_PSI_1, // Phase count 1st level
177 SVI_PSI_2, // Phase count 2nd level
178 SVI_PSI_3, // Single phase operation + active diode emulation
179 SVI_PSI_4, // Single phase operation + passive diode emulation *optional*
182 SVI_PSI_7, // Automated phase shedding and diode emulation
503 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
506 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
1007 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1008 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_sp.h3 * Copyright 2011-2013 Broadcom Corporation
10 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
45 * re-try to submit this one. This flag can be set only in sleepable
101 /************************* VLAN-MAC commands related parameters ***************/
178 /* Return positive if entry was optimized, 0 - if not, negative
211 * Must run under exe_queue->lock
227 * Must run under exe_queue->lock
242 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
250 /* Used to store the cam offset used for the mac/vlan/vlan-mac.
322 * will be copied. Note elements are 4-byte aligned
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