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/linux/drivers/pci/controller/
H A Dpcie-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/irqchip/irq-msi-lib.h>
39 /* PCIe per port registers */
75 /* PCIe V2 per-port registers */
128 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
146 * enum mtk_pcie_quirks - MT
188 void __iomem *base; global() member
218 void __iomem *base; global() member
236 mtk_pcie_port_free(struct mtk_pcie_port * port) mtk_pcie_port_free() argument
248 struct mtk_pcie_port *port, *tmp; mtk_pcie_put_resources() local
265 mtk_pcie_check_cfg_cpld(struct mtk_pcie_port * port) mtk_pcie_check_cfg_cpld() argument
282 mtk_pcie_hw_rd_cfg(struct mtk_pcie_port * port,u32 bus,u32 devfn,int where,int size,u32 * val) mtk_pcie_hw_rd_cfg() argument
314 mtk_pcie_hw_wr_cfg(struct mtk_pcie_port * port,u32 bus,u32 devfn,int where,int size,u32 val) mtk_pcie_hw_wr_cfg() argument
341 struct mtk_pcie_port *port; mtk_pcie_find_port() local
364 struct mtk_pcie_port *port; mtk_pcie_config_read() local
377 struct mtk_pcie_port *port; mtk_pcie_config_write() local
394 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); mtk_compose_msi_msg() local
410 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); mtk_msi_ack_irq() local
425 struct mtk_pcie_port *port = domain->host_data; mtk_pcie_irq_domain_alloc() local
452 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d); mtk_pcie_irq_domain_free() local
488 mtk_pcie_allocate_msi_domains(struct mtk_pcie_port * port) mtk_pcie_allocate_msi_domains() argument
508 mtk_pcie_enable_msi(struct mtk_pcie_port * port) mtk_pcie_enable_msi() argument
524 struct mtk_pcie_port *port, *tmp; mtk_pcie_irq_teardown() local
554 mtk_pcie_init_irq_domain(struct mtk_pcie_port * port,struct device_node * node) mtk_pcie_init_irq_domain() argument
587 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); mtk_pcie_intr_handler() local
626 mtk_pcie_setup_irq(struct mtk_pcie_port * port,struct device_node * node) mtk_pcie_setup_irq() argument
654 mtk_pcie_startup_port_v2(struct mtk_pcie_port * port) mtk_pcie_startup_port_v2() argument
764 mtk_pcie_startup_port(struct mtk_pcie_port * port) mtk_pcie_startup_port() argument
824 mtk_pcie_enable_port(struct mtk_pcie_port * port) mtk_pcie_enable_port() argument
909 struct mtk_pcie_port *port; mtk_pcie_parse_port() local
1041 struct mtk_pcie_port *port, *tmp; mtk_pcie_setup() local
1143 struct mtk_pcie_port *port; mtk_pcie_suspend_noirq() local
1167 struct mtk_pcie_port *port, *tmp; mtk_pcie_resume_noirq() local
[all...]
H A Dpcie-apple.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host bridge driver for Apple system-on-chips.
6 * the driver mostly deals MSI mapping and handling of per-port
26 #include <linux/irqchip/irq-msi-lib.h>
32 #include <linux/pci-eca
48 CORE_PHY_DEFAULT_BASE(port) global() argument
186 void __iomem *base; global() member
200 void __iomem *base; global() member
291 struct apple_pcie_port *port = irq_data_get_irq_chip_data(data); apple_port_irq_mask() local
299 struct apple_pcie_port *port = irq_data_get_irq_chip_data(data); apple_port_irq_unmask() local
312 struct apple_pcie_port *port = irq_data_get_irq_chip_data(data); apple_port_irq_ack() local
344 struct apple_pcie_port *port = domain->host_data; apple_port_irq_domain_alloc() local
388 struct apple_pcie_port *port = irq_desc_get_handler_data(desc); apple_port_irq_handler() local
403 apple_pcie_port_setup_irq(struct apple_pcie_port * port) apple_pcie_port_setup_irq() argument
453 struct apple_pcie_port *port = data; apple_pcie_port_irq() local
473 apple_pcie_port_register_irqs(struct apple_pcie_port * port) apple_pcie_port_register_irqs() argument
509 apple_pcie_setup_refclk(struct apple_pcie * pcie,struct apple_pcie_port * port) apple_pcie_setup_refclk() argument
544 port_rid2sid_addr(struct apple_pcie_port * port,int idx) port_rid2sid_addr() argument
549 apple_pcie_rid2sid_write(struct apple_pcie_port * port,int idx,u32 val) apple_pcie_rid2sid_write() argument
561 struct apple_pcie_port *port; apple_pcie_setup_port() local
760 struct apple_pcie_port *port; apple_pcie_get_port() local
784 struct apple_pcie_port *port; apple_pcie_enable_device() local
818 struct apple_pcie_port *port; apple_pcie_disable_device() local
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H A Dpci-mvebu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
27 #include "../pci-bridge-emul.h"
40 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
94 phys_addr_t base; member
102 void __iomem *base; member
103 u32 port; member
128 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg) in mvebu_writel() argument
130 writel(val, port->base + reg); in mvebu_writel()
133 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg) in mvebu_readl() argument
[all …]
H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
258 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
259 * entries, one entry per PCIe port. These field definitions and desired
368 void __iomem *base; member
380 writel(value, pcie->afi + offset); in afi_writel()
385 return readl(pcie->afi + offset); in afi_readl()
391 writel(value, pcie->pads + offset); in pads_writel()
[all …]
/linux/drivers/gpio/
H A Dgpio-mxc.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
63 void __iomem *base; member
88 .edge_sel_reg = -EINVAL,
103 .edge_sel_reg = -EINVAL,
125 #define GPIO_DR (port->hwdata->dr_reg)
126 #define GPIO_GDIR (port->hwdata->gdir_reg)
127 #define GPIO_PSR (port->hwdata->psr_reg)
128 #define GPIO_ICR1 (port->hwdata->icr1_reg)
129 #define GPIO_ICR2 (port->hwdata->icr2_reg)
[all …]
H A Dgpio-gpio-mm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the Diamond Systems GPIO-MM
6 * This driver supports the following Diamond Systems devices: GPIO-MM and
7 * GPIO-MM-12.
19 #include "gpio-i8255.h"
26 static unsigned int base[MAX_NUM_GPIOMM]; variable
28 module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
29 MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
52 "Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
53 "Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
[all …]
H A Dgpio-ws16c48.c1 // SPDX-License-Identifier: GPL-2.0-only
23 static unsigned int base[MAX_NUM_WS16C48]; variable
25 module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
26 MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
89 /* Only the first 24 lines (Port 0-2) support interrupts */
92 WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0-2 */
93 WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3-5 */
94 WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6-8 */
95 WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /* 9-11 */
96 WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /* 12-14 */
[all …]
H A Dgpio-104-dio-48e.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the ACCES 104-DIO-48E series
6 * This driver supports the following ACCES devices: 104-DIO-48E and
7 * 104-DIO-24E.
23 #include "gpio-i8255.h"
30 static unsigned int base[MAX_NUM_DIO48E]; variable
32 module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
33 MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
38 MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
98 /* only bit 3 on each respective Port C supports interrupts */
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-csi-0-5.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/phy/phy.h>
19 #include "phy-mtk-io.h"
20 #include "phy-mtk-mipi-csi-0-5-rx-reg.h"
26 void __iomem *base; member
39 static void mtk_phy_csi_cdphy_ana_eq_tune(void __iomem *base) in mtk_phy_csi_cdphy_ana_eq_tune() argument
41 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
42 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
43 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
44 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-jsl-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
11 #include "ipu6-bus.h"
12 #include "ipu6-isys.h"
13 #include "ipu6-isys-csi2.h"
14 #include "ipu6-platform-isys-csi2-reg.h"
27 * +---------+ +------+ +-----+
28 * | port0 x4<-----| | | |
29 * | | | port | | |
30 * | port1 x2<-----| | | |
[all …]
/linux/drivers/phy/tegra/
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
H A Dxusb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
19 /* legacy entry points for backwards-compatibility */
59 struct tegra_xusb_lane base; member
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
69 struct tegra_xusb_lane base; member
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
82 struct tegra_xusb_lane base; member
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
92 struct tegra_xusb_lane base; member
[all …]
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
214 struct tegra_xusb_padctl base; member
222 return container_of(padctl, struct tegra124_xusb_padctl, base); in to_tegra124_xusb_padctl()
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
[all …]
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 struct ehea_port *port = netdev_priv(dev); in ehea_get_link_ksettings() local
28 ret = ehea_sense_port_attr(port); in ehea_get_link_ksettings()
34 switch (port->port_speed) { in ehea_get_link_ksettings()
48 speed = -1; in ehea_get_link_ksettings()
51 cmd->base.duplex = port->full_duplex == 1 ? in ehea_get_link_ksettings()
55 cmd->base.duplex = DUPLEX_UNKNOWN; in ehea_get_link_ksettings()
57 cmd->base.speed = speed; in ehea_get_link_ksettings()
59 if (cmd->base.speed == SPEED_10000) { in ehea_get_link_ksettings()
[all …]
/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
25 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-owl.h"
35 * struct owl_pinctrl - pinctrl state of the device
42 * @base: pinctrl register base address
53 void __iomem *base; member
58 static void owl_update_bits(void __iomem *base, u32 mask, u32 val) in owl_update_bits() argument
62 reg_val = readl_relaxed(base); in owl_update_bits()
[all …]
/linux/drivers/tty/
H A Dgoldfish.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/dma-mapping.h>
37 struct tty_port port; member
39 void __iomem *base; member
57 void __iomem *base = qtty->base; in do_rw_io() local
59 spin_lock_irqsave(&qtty->lock, irq_flags); in do_rw_io()
60 gf_write_ptr((void *)address, base + GOLDFISH_TTY_REG_DATA_PTR, in do_rw_io()
61 base + GOLDFISH_TTY_REG_DATA_PTR_HIGH); in do_rw_io()
62 gf_iowrite32(count, base + GOLDFISH_TTY_REG_DATA_LEN); in do_rw_io()
66 base + GOLDFISH_TTY_REG_CMD); in do_rw_io()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
[all …]
/linux/Documentation/networking/dsa/
H A Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_taprio.c1 // SPDX-License-Identifier: GPL-2.0+
12 #define LAN966X_TAPRIO_MAX_CYCLE_TIME_NS (NSEC_PER_SEC - 1)
41 static u32 lan966x_taprio_list_index(struct lan966x_port *port, u8 entry) in lan966x_taprio_list_index() argument
43 return port->chip_port * LAN966X_TAPRIO_ENTRIES_PER_PORT + entry; in lan966x_taprio_list_index()
46 static u32 lan966x_taprio_list_state_get(struct lan966x_port *port) in lan966x_taprio_list_state_get() argument
48 struct lan966x *lan966x = port->lan966x; in lan966x_taprio_list_state_get()
55 static u32 lan966x_taprio_list_index_state_get(struct lan966x_port *port, in lan966x_taprio_list_index_state_get() argument
58 struct lan966x *lan966x = port->lan966x; in lan966x_taprio_list_index_state_get()
64 return lan966x_taprio_list_state_get(port); in lan966x_taprio_list_index_state_get()
67 static void lan966x_taprio_list_state_set(struct lan966x_port *port, in lan966x_taprio_list_state_set() argument
[all …]
/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Shan-Chun Hung <schung@nuvoton.com>
24 #include "pinctrl-ma35.h"
59 /* GPIO pull-up and pull-down selection control */
66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67 * while bits 16 ~ 31 control high-level or rising edge trigger.
75 * register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3
145 return npctl->ngroups; in ma35_get_groups_count()
152 return npctl->groups[selector].grp.name; in ma35_get_group_name()
160 if (selector >= npctl->ngroups) in ma35_get_group_pins()
[all …]
/linux/Documentation/driver-api/cxl/platform/
H A Dcdat.rst1 .. SPDX-License-Identifier: GPL-2.0
13 DPA - Device Physical Address, used by the CXL device to denote the address
16 DSMADHandle - A device unique handle that is associated with a DPA range
24 The DSMAS contains information such as DSMADHandle, the DPA Base, and DPA
35 Length : 0018 <- 24d, size of structure
39 DPA Base : 0000000040000000 <- 1GiB base
40 DPA Length : 0000000080000000 <- 2GiB size
55 Length : 18 <- 24d, size of structure
56 Handle : 0001 <- DSMAS handle
57 Flags : 00 <- Matches flag field for HMAT SLLBIS
[all …]
/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_ethtool.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2019-2020 Marvell International Ltd. All rights reserved */
300 struct prestera_port *port = netdev_priv(dev); in prestera_ethtool_get_drvinfo() local
301 struct prestera_switch *sw = port->sw; in prestera_ethtool_get_drvinfo()
303 strscpy(drvinfo->driver, driver_kind, sizeof(drvinfo->driver)); in prestera_ethtool_get_drvinfo()
304 strscpy(drvinfo->bus_info, dev_name(prestera_dev(sw)), in prestera_ethtool_get_drvinfo()
305 sizeof(drvinfo->bus_info)); in prestera_ethtool_get_drvinfo()
306 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), in prestera_ethtool_get_drvinfo()
308 sw->dev->fw_rev.maj, in prestera_ethtool_get_drvinfo()
309 sw->dev->fw_rev.min, in prestera_ethtool_get_drvinfo()
[all …]
/linux/drivers/net/ethernet/ti/
H A Dnetcp_sgmii.c1 // SPDX-License-Identifier: GPL-2.0
7 * Sandeep Paulraj <s-paulraj@ti.com>
8 * Wingman Kwok <w-kwok2@ti.com>
22 #define SGMII23_OFFSET(x) ((x - 2) * 0x100)
31 static void sgmii_write_reg(void __iomem *base, int reg, u32 val) in sgmii_write_reg() argument
33 writel(val, base + reg); in sgmii_write_reg()
36 static u32 sgmii_read_reg(void __iomem *base, int reg) in sgmii_read_reg() argument
38 return readl(base + reg); in sgmii_read_reg()
41 static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val) in sgmii_write_reg_bit() argument
43 writel((readl(base + reg) | val), base + reg); in sgmii_write_reg_bit()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Daudio-graph-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Audio Graph Card 'port'
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
17 - $ref: /schemas/graph.yaml#/$defs/port-base
18 - $ref: /schemas/sound/dai-params.yaml#
20 mclk-fs:
[all …]
/linux/drivers/ata/
H A Dpata_icside.c1 // SPDX-License-Identifier: GPL-2.0-only
59 } port[2]; member
65 void __iomem *base; member
71 const struct portinfo *port[2]; member
80 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
82 /* ---------------- Version 5 PCB Support Functions --------------------- */
88 struct pata_icside_state *state = ec->irq_data; in pata_icside_irqenable_arcin_v5()
90 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET); in pata_icside_irqenable_arcin_v5()
98 struct pata_icside_state *state = ec->irq_data; in pata_icside_irqdisable_arcin_v5()
100 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET); in pata_icside_irqdisable_arcin_v5()
[all …]

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