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/linux/drivers/gpio/
H A Dgpio-mxs.c1 // SPDX-License-Identifier: GPL-2.0+
7 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
25 #define PINCTRL_DOUT(p) ((is_imx23_gpio(p) ? 0x0500 : 0x0700) + (p->id) * 0x10)
26 #define PINCTRL_DIN(p) ((is_imx23_gpio(p) ? 0x0600 : 0x0900) + (p->id) * 0x10)
27 #define PINCTRL_DOE(p) ((is_imx23_gpio(p) ? 0x0700 : 0x0b00) + (p->id) * 0x10)
28 #define PINCTRL_PIN2IRQ(p) ((is_imx23_gpio(p) ? 0x0800 : 0x1000) + (p->id) * 0x10)
29 #define PINCTRL_IRQEN(p) ((is_imx23_gpio(p) ? 0x0900 : 0x1100) + (p->id) * 0x10)
30 #define PINCTRL_IRQLEV(p) ((is_imx23_gpio(p) ? 0x0a00 : 0x1200) + (p->id) * 0x10)
31 #define PINCTRL_IRQPOL(p) ((is_imx23_gpio(p) ? 0x0b00 : 0x1300) + (p->id) * 0x10)
32 #define PINCTRL_IRQSTAT(p) ((is_imx23_gpio(p) ? 0x0c00 : 0x1400) + (p->id) * 0x10)
[all …]
H A Dgpio-mxc.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
61 void __iomem *base; member
86 .edge_sel_reg = -EINVAL,
101 .edge_sel_reg = -EINVAL,
123 #define GPIO_DR (port->hwdata->dr_reg)
124 #define GPIO_GDIR (port->hwdata->gdir_reg)
125 #define GPIO_PSR (port->hwdata->psr_reg)
126 #define GPIO_ICR1 (port->hwdata->icr1_reg)
127 #define GPIO_ICR2 (port->hwdata->icr2_reg)
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H A Dgpio-vf610.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale vf610 GPIO support through PORT and GPIO
25 /* SoCs has a Port Data Direction Register (PDDR) */
32 void __iomem *base; member
81 { .compatible = "fsl,vf610-gpio", .data = &vf610_data },
82 { .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
83 { .compatible = "fsl,imx8ulp-gpio", .data = &imx8ulp_data, },
99 struct vf610_gpio_port *port = gpiochip_get_data(gc); in vf610_gpio_get() local
103 if (port->sdata->have_paddr) { in vf610_gpio_get()
104 mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR); in vf610_gpio_get()
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H A Dgpio-gpio-mm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * GPIO driver for the Diamond Systems GPIO-MM
6 * This driver supports the following Diamond Systems devices: GPIO-MM and
7 * GPIO-MM-12.
19 #include "gpio-i8255.h"
26 static unsigned int base[MAX_NUM_GPIOMM]; variable
28 module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
29 MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
52 "Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
53 "Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-csi-0-5.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/phy/phy.h>
19 #include "phy-mtk-io.h"
20 #include "phy-mtk-mipi-csi-0-5-rx-reg.h"
26 void __iomem *base; member
39 static void mtk_phy_csi_cdphy_ana_eq_tune(void __iomem *base) in mtk_phy_csi_cdphy_ana_eq_tune() argument
41 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
42 mtk_phy_update_field(base + MIPI_RX_ANA18_CSIXA, RG_CSI0A_L0_T0AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
43 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_IS, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
44 mtk_phy_update_field(base + MIPI_RX_ANA1C_CSIXA, RG_CSI0A_L1_T1AB_EQ_BW, 1); in mtk_phy_csi_cdphy_ana_eq_tune()
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/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-isys-jsl-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
11 #include "ipu6-bus.h"
12 #include "ipu6-isys.h"
13 #include "ipu6-isys-csi2.h"
14 #include "ipu6-platform-isys-csi2-reg.h"
27 * +---------+ +------+ +-----+
28 * | port0 x4<-----| | | |
29 * | | | port | | |
30 * | port1 x2<-----| | | |
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/linux/drivers/phy/tegra/
H A Dxusb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
19 /* legacy entry points for backwards-compatibility */
59 struct tegra_xusb_lane base; member
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
69 struct tegra_xusb_lane base; member
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
82 struct tegra_xusb_lane base; member
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
92 struct tegra_xusb_lane base; member
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H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
214 struct tegra_xusb_padctl base; member
222 return container_of(padctl, struct tegra124_xusb_padctl, base); in to_tegra124_xusb_padctl()
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dvo.c3 * Copyright © 2006-2007 Intel Corporation
63 .port = PORT_C,
70 .port = PORT_C,
77 .port = PORT_C,
84 .port = PORT_A,
91 .port = PORT_C,
98 .port = PORT_C,
106 .port = PORT_B,
113 struct intel_encoder base; member
122 return container_of(encoder, struct intel_dvo, base); in enc_to_dvo()
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H A Dintel_ddi.c101 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
103 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
119 * Starting with Haswell, DDI port buffers must be programmed with correct
126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
129 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers() local
132 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
133 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
138 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
142 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i), in hsw_prepare_dp_ddi_buffers()
143 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
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H A Dintel_tc.c1 // SPDX-License-Identifier: MIT
52 struct mutex lock; /* protects the TypeC port mode */
79 [TC_PORT_TBT_ALT] = "tbt-alt", in tc_port_mode_name()
80 [TC_PORT_DP_ALT] = "dp-alt", in tc_port_mode_name()
92 return dig_port->tc; in to_tc_port()
97 return to_i915(tc->dig_port->base.base.dev); in tc_to_i915()
105 return intel_encoder_is_tc(&dig_port->base) && tc->mode == mode; in intel_tc_port_in_mode()
127 return intel_encoder_is_tc(&dig_port->base) && !tc->legacy_port; in intel_tc_port_handles_hpd_glitches()
132 * platform and TC mode (legacy, DP-alt, TBT):
135 * --------------------------
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H A Dintel_audio.c43 * DOC: High Definition Audio over HDMI and Display Port
46 * HDMI and Display Port. The audio programming sequences are divided into audio
52 * port. The enable sequences may only be performed after enabling the
53 * transcoder and port, and after completed link training. Therefore the audio
59 * co-operation between the graphics and audio drivers is handled via audio
144 /* Appendix C - N & CTS values for deep color from HDMI 2.0 spec*/
199 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in audio_config_hdmi_pixel_clock()
201 &crtc_state->hw.adjusted_mode; in audio_config_hdmi_pixel_clock()
205 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock) in audio_config_hdmi_pixel_clock()
209 if (DISPLAY_VER(i915) < 12 && adjusted_mode->crtc_clock > 148500) in audio_config_hdmi_pixel_clock()
[all …]
/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 struct ehea_port *port = netdev_priv(dev); in ehea_get_link_ksettings() local
28 ret = ehea_sense_port_attr(port); in ehea_get_link_ksettings()
34 switch (port->port_speed) { in ehea_get_link_ksettings()
48 speed = -1; in ehea_get_link_ksettings()
51 cmd->base.duplex = port->full_duplex == 1 ? in ehea_get_link_ksettings()
55 cmd->base.duplex = DUPLEX_UNKNOWN; in ehea_get_link_ksettings()
57 cmd->base.speed = speed; in ehea_get_link_ksettings()
59 if (cmd->base.speed == SPEED_10000) { in ehea_get_link_ksettings()
[all …]
/linux/drivers/pinctrl/actions/
H A Dpinctrl-owl.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
25 #include <linux/pinctrl/pinconf-generic.h>
31 #include "../pinctrl-utils.h"
32 #include "pinctrl-owl.h"
35 * struct owl_pinctrl - pinctrl state of the device
42 * @base: pinctrl register base address
53 void __iomem *base; member
58 static void owl_update_bits(void __iomem *base, u32 mask, u32 val) in owl_update_bits() argument
62 reg_val = readl_relaxed(base); in owl_update_bits()
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/linux/drivers/tty/
H A Dgoldfish.c1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/dma-mapping.h>
37 struct tty_port port; member
39 void __iomem *base; member
57 void __iomem *base = qtty->base; in do_rw_io() local
59 spin_lock_irqsave(&qtty->lock, irq_flags); in do_rw_io()
60 gf_write_ptr((void *)address, base + GOLDFISH_TTY_REG_DATA_PTR, in do_rw_io()
61 base + GOLDFISH_TTY_REG_DATA_PTR_HIGH); in do_rw_io()
62 gf_iowrite32(count, base + GOLDFISH_TTY_REG_DATA_LEN); in do_rw_io()
66 base + GOLDFISH_TTY_REG_CMD); in do_rw_io()
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/linux/drivers/hsi/controllers/
H A Domap_ssi_port.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* OMAP SSI port driver.
12 #include <linux/dma-mapping.h>
33 static inline unsigned int ssi_wakein(struct hsi_port *port) in ssi_wakein() argument
35 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); in ssi_wakein()
36 return gpiod_get_value(omap_port->wake_gpio); in ssi_wakein()
40 static void ssi_debug_remove_port(struct hsi_port *port) in ssi_debug_remove_port() argument
42 struct omap_ssi_port *omap_port = hsi_port_drvdata(port); in ssi_debug_remove_port()
44 debugfs_remove_recursive(omap_port->dir); in ssi_debug_remove_port()
49 struct hsi_port *port = m->private; in ssi_port_regs_show() local
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/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hns-dsaf.txt4 - compatible: should be "hisilicon,hns-dsaf-v1" or "hisilicon,hns-dsaf-v2".
5 "hisilicon,hns-dsaf-v1" is for hip05.
6 "hisilicon,hns-dsaf-v2" is for Hi1610 and Hi1612.
7 - mode: dsa fabric mode string. only support one of dsaf modes like these:
8 "2port-64vf",
9 "6port-16rss",
10 "6port-16vf",
11 "single-port".
12 - interrupts: should contain the DSA Fabric and rcb interrupt.
13 - reg: specifies base physical address(es) and size of the device registers.
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/linux/Documentation/networking/dsa/
H A Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
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/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_taprio.c1 // SPDX-License-Identifier: GPL-2.0+
12 #define LAN966X_TAPRIO_MAX_CYCLE_TIME_NS (NSEC_PER_SEC - 1)
41 static u32 lan966x_taprio_list_index(struct lan966x_port *port, u8 entry) in lan966x_taprio_list_index() argument
43 return port->chip_port * LAN966X_TAPRIO_ENTRIES_PER_PORT + entry; in lan966x_taprio_list_index()
46 static u32 lan966x_taprio_list_state_get(struct lan966x_port *port) in lan966x_taprio_list_state_get() argument
48 struct lan966x *lan966x = port->lan966x; in lan966x_taprio_list_state_get()
55 static u32 lan966x_taprio_list_index_state_get(struct lan966x_port *port, in lan966x_taprio_list_index_state_get() argument
58 struct lan966x *lan966x = port->lan966x; in lan966x_taprio_list_index_state_get()
64 return lan966x_taprio_list_state_get(port); in lan966x_taprio_list_index_state_get()
67 static void lan966x_taprio_list_state_set(struct lan966x_port *port, in lan966x_taprio_list_state_set() argument
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/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Shan-Chun Hung <schung@nuvoton.com>
24 #include "pinctrl-ma35.h"
59 /* GPIO pull-up and pull-down selection control */
66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
67 * while bits 16 ~ 31 control high-level or rising edge trigger.
75 * register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3
84 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
85 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
86 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
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/linux/drivers/hwtracing/coresight/
H A Dcoresight-tpda.c1 // SPDX-License-Identifier: GPL-2.0
18 #include "coresight-priv.h"
19 #include "coresight-tpda.h"
20 #include "coresight-trace-id.h"
21 #include "coresight-tpdm.h"
28 (csdev->subtype.source_subtype == in coresight_device_is_tpdm()
34 struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->de in tpda_clear_element_size()
142 tpda_enable_port(struct tpda_drvdata * drvdata,int port) tpda_enable_port() argument
165 __tpda_enable(struct tpda_drvdata * drvdata,int port) __tpda_enable() argument
206 __tpda_disable(struct tpda_drvdata * drvdata,int port) __tpda_disable() argument
269 void __iomem *base; tpda_probe() local
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/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_ethtool.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2019-2020 Marvell International Ltd. All rights reserved */
300 struct prestera_port *port = netdev_priv(dev); in prestera_ethtool_get_drvinfo() local
301 struct prestera_switch *sw = port->sw; in prestera_ethtool_get_drvinfo()
303 strscpy(drvinfo->driver, driver_kind, sizeof(drvinfo->driver)); in prestera_ethtool_get_drvinfo()
304 strscpy(drvinfo->bus_info, dev_name(prestera_dev(sw)), in prestera_ethtool_get_drvinfo()
305 sizeof(drvinfo->bus_info)); in prestera_ethtool_get_drvinfo()
306 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), in prestera_ethtool_get_drvinfo()
308 sw->dev->fw_rev.maj, in prestera_ethtool_get_drvinfo()
309 sw->dev->fw_rev.min, in prestera_ethtool_get_drvinfo()
[all …]
/linux/drivers/fpga/
H A Ddfl-afu-error.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/fpga-dfl.h>
20 #include "dfl-afu.h"
30 /* mask or unmask port errors by the error mask register. */
33 void __iomem *base; in __afu_port_err_mask() local
35 base = dfl_get_feature_ioaddr_by_id(fdata, PORT_FEATURE_ID_ERROR); in __afu_port_err_mask()
37 writeq(mask ? ERROR_MASK : 0, base + PORT_ERROR_MASK); in __afu_port_err_mask()
44 mutex_lock(&fdata->loc in afu_port_err_mask()
119 void __iomem *base; errors_show() local
150 void __iomem *base; first_error_show() local
168 void __iomem *base; first_malformed_req_show() local
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/linux/drivers/net/ethernet/ti/
H A Dnetcp_sgmii.c1 // SPDX-License-Identifier: GPL-2.0
7 * Sandeep Paulraj <s-paulraj@ti.com>
8 * Wingman Kwok <w-kwok2@ti.com>
22 #define SGMII23_OFFSET(x) ((x - 2) * 0x100)
31 static void sgmii_write_reg(void __iomem *base, int reg, u32 val) in sgmii_write_reg() argument
33 writel(val, base + reg); in sgmii_write_reg()
36 static u32 sgmii_read_reg(void __iomem *base, int reg) in sgmii_read_reg() argument
38 return readl(base + reg); in sgmii_read_reg()
41 static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val) in sgmii_write_reg_bit() argument
43 writel((readl(base + reg) | val), base + reg); in sgmii_write_reg_bit()
[all …]
/linux/drivers/phy/marvell/
H A Dphy-mvebu-cp110-comphy.c1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
8 #include <linux/arm-smccc.h>
20 /* Relative to priv->base */
108 /* Relative to priv->regmap */
130 * [ 1- 0]: COMPHY polarity invertion
131 * [ 2-
154 COMPHY_FW_PARAM_FULL(mode,port,speed,pol,width) global() argument
161 COMPHY_FW_PARAM(mode,port) global() argument
164 COMPHY_FW_PARAM_ETH(mode,port,speed) global() argument
167 COMPHY_FW_PARAM_PCIE(mode,port,width) global() argument
183 unsigned port; global() member
259 void __iomem *base; global() member
273 int port; global() member
295 mvebu_comphy_get_mode(bool fw_mode,int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_mode() argument
325 mvebu_comphy_get_mux(int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_mux() argument
331 mvebu_comphy_get_fw_mode(int lane,int port,enum phy_mode mode,int submode) mvebu_comphy_get_fw_mode() argument
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