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Searched full:pllclk (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dsophgo,sg2042-clkgen.yaml52 clocks = <&pllclk 0>,
53 <&pllclk 1>,
54 <&pllclk 2>,
55 <&pllclk 3>;
H A Dstarfive,jh7110-syscrg.yaml109 <&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
/linux/arch/mips/pic32/pic32mzda/
H A Dearly_clk.c31 u32 pllclk; in pic32_get_sysclk() local
54 pllclk = plliclk ? FRC_CLK : PIC32_POSC_FREQ; in pic32_get_sysclk()
72 osc_freq = ((pllclk / pllidiv) * pllmult) / pllodiv; in pic32_get_sysclk()
/linux/drivers/clk/
H A Dclk-xgene.c61 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_is_enabled() local
64 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
74 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_recalc_rate() local
82 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
84 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
85 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
114 pllclk->version); in xgene_clk_pll_recalc_rate()
/linux/Documentation/devicetree/bindings/display/bridge/
H A Drenesas,dsi.yaml62 - const: pllclk
156 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
207 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
/linux/include/dt-bindings/clock/
H A Dmicrochip,pic32-clock.h17 #define PLLCLK 6 macro
/linux/drivers/clk/microchip/
H A Dclk-pic32mzda.c208 clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core); in pic32mzda_clk_probe()
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g054.dtsi909 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
H A Dr9a07g044.dtsi904 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";