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Searched full:pllc2 (Results 1 – 6 of 6) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Drenesas,r8a7740-cpg-clocks.txt17 "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
32 "pllc2", "r",
H A Drenesas,cpg-clocks.yaml108 - const: pllc2
237 clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
/freebsd/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_subr.c3565 uint32_t pllc1, pllc2; in bhnd_pmu_set_4330_plldivs() local
3583 pllc2 = 0; in bhnd_pmu_set_4330_plldivs()
3584 pllc2 |= BHND_PMU_SET_BITS(m5div, BHND_PMU1_PLL0_PC2_M5DIV); in bhnd_pmu_set_4330_plldivs()
3585 pllc2 |= BHND_PMU_SET_BITS(m6div, BHND_PMU1_PLL0_PC2_M6DIV); in bhnd_pmu_set_4330_plldivs()
3587 BHND_PMU_PLL_WRITE(sc, BHND_PMU1_PLL0_PLLCTL2, pllc2, in bhnd_pmu_set_4330_plldivs()
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c127 PLLC2: Clock source for engine scaling
253 /* PLLC2: 600 MHz Clock source for engine scaling */
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a7740.dtsi550 "pllc2", "r",
/freebsd/sys/arm64/nvidia/tegra210/
H A Dtegra210_clk_pll.c317 /* PLLC2: 510 MHz Clock source for SE, VIC, TSECB, NVJPG scaling */