Searched full:plla_out0 (Results 1 – 3 of 3) sorted by relevance
104 * |--> PLLA_OUT0 in tegra_audio_graph_update_pll()113 * Default PLLA_OUT0 rate might be too high when I/O is running in tegra_audio_graph_update_pll()116 * and any thing higher than that won't work. Thus reduce PLLA_OUT0 in tegra_audio_graph_update_pll()127 "Update clock rates: PLLA(= %u Hz) and PLLA_OUT0(= %u Hz)\n", in tegra_audio_graph_update_pll()139 /* Set PLLA_OUT0 rate */ in tegra_audio_graph_update_pll()143 "Can't set plla_out0 rate %u, err: %d\n", in tegra_audio_graph_update_pll()184 priv->clk_plla_out0 = devm_clk_get(card->dev, "plla_out0"); in tegra_audio_graph_card_probe()187 "can't retrieve clk plla_out0\n"); in tegra_audio_graph_card_probe()223 /* PLLA_OUT0 */232 /* PLLA_OUT0 */[all …]
35 - const: plla_out079 clock-names = "pll_a", "plla_out0";
190 /* PLLA_OUT0 */ in tegra_audio_clk_init()