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Searched full:pll_u (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml62 - const: pll_u
66 - const: pll_u
71 - const: pll_u
76 - const: pll_u
270 - const: pll_u
286 - const: pll_u
312 - const: pll_u
316 - const: pll_u
340 clock-names = "reg", "pll_u", "utmi-pads";
368 clock-names = "reg", "pll_u", "ulpi-link";
/linux/drivers/usb/phy/
H A Dphy-tegra-usb.c861 clk_disable_unprepare(phy->pll_u); in tegra_usb_phy_shutdown()
1018 err = clk_prepare_enable(phy->pll_u); in tegra_usb_phy_init()
1022 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); in tegra_usb_phy_init()
1030 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n", in tegra_usb_phy_init()
1067 clk_disable_unprepare(phy->pll_u); in tegra_usb_phy_init()
1304 tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u"); in tegra_usb_phy_probe()
1305 err = PTR_ERR_OR_ZERO(tegra_phy->pll_u); in tegra_usb_phy_probe()
1307 dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err); in tegra_usb_phy_probe()
/linux/include/linux/usb/
H A Dtegra_usb_phy.h65 struct clk *pll_u; member
/linux/drivers/clk/tegra/
H A Dclk-tegra114.c829 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
948 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra114_pll_init()
953 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", in tegra114_pll_init()
959 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", in tegra114_pll_init()
964 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", in tegra114_pll_init()
969 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", in tegra114_pll_init()
H A Dclk-tegra124.c954 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
1148 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra124_pll_init()
1150 clk_register_clkdev(clk, "pll_u", NULL); in tegra124_pll_init()
1154 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", in tegra124_pll_init()
1161 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", in tegra124_pll_init()
1167 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", in tegra124_pll_init()
1173 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", in tegra124_pll_init()
H A Dclk-tegra20.c430 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
663 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
H A Dclk-tegra30.c550 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
847 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, in tegra30_pll_init()
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20.dtsi872 clock-names = "reg", "pll_u", "timer", "utmi-pads";
911 clock-names = "reg", "pll_u", "ulpi-link";
943 clock-names = "reg", "pll_u", "timer", "utmi-pads";
H A Dtegra30.dtsi1134 clock-names = "reg", "pll_u", "utmi-pads";
1177 clock-names = "reg", "pll_u", "utmi-pads";
1219 clock-names = "reg", "pll_u", "utmi-pads";
H A Dtegra124.dtsi1129 clock-names = "reg", "pll_u", "utmi-pads";
1169 clock-names = "reg", "pll_u", "utmi-pads";
1208 clock-names = "reg", "pll_u", "utmi-pads";
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi1020 clock-names = "reg", "pll_u", "utmi-pads";
1061 clock-names = "reg", "pll_u", "utmi-pads";
1101 clock-names = "reg", "pll_u", "utmi-pads";
H A Dtegra210.dtsi1909 clock-names = "reg", "pll_u", "utmi-pads";
1947 clock-names = "reg", "pll_u", "utmi-pads";