Searched full:pll_reset_n (Results 1 – 4 of 4) sorted by relevance
| /linux/drivers/clk/qcom/ |
| H A D | clk-pll.c | 22 #define PLL_RESET_N BIT(2) macro
30 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
53 PLL_RESET_N); in clk_pll_enable()
75 mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL; in clk_pll_disable()
147 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_set_rate()
286 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_sr2_enable()
287 PLL_RESET_N); in clk_pll_sr2_enable()
307 u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N; in clk_pll_sr2_set_rate()
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| H A D | clk-hfpll.c | 17 #define PLL_RESET_N BIT(2) macro
76 regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N); in __clk_hfpll_enable()
105 if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL))) in clk_hfpll_enable()
122 PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0); in __clk_hfpll_disable()
214 if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) { in clk_hfpll_init()
241 return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL); in hfpll_is_enabled()
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | qcom,qcs615-tlmm.yaml | 86 pll_bypassnl, pll_reset_n, prng_rosc, qdss_cti, qdss_gpio,
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| /linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-qcs615.c | 873 MSM_PIN_FUNCTION(pll_reset_n),
920 [14] = PINGROUP(14, EAST, qup1, pll_reset_n, _, qdss_gpio, _, _, _, _, _),
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