Searched full:pll_ref_clk (Results 1 – 12 of 12) sorted by relevance
| /linux/drivers/phy/cadence/ |
| H A D | cdns-dphy.c | 108 struct clk *pll_ref_clk; member
124 unsigned long pll_ref_hz = clk_get_rate(dphy->pll_ref_clk); in cdns_dsi_get_dphy_pll_cfg()
384 clk_prepare_enable(dphy->pll_ref_clk); in cdns_dphy_power_on()
397 clk_disable_unprepare(dphy->pll_ref_clk); in cdns_dphy_power_off()
433 dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref"); in cdns_dphy_probe()
434 if (IS_ERR(dphy->pll_ref_clk)) in cdns_dphy_probe()
435 return PTR_ERR(dphy->pll_ref_clk); in cdns_dphy_probe()
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| /linux/drivers/usb/dwc3/ |
| H A D | dwc3-octeon.c | 34 * HighSpeed PLL uses PLL_REF_CLK for reference clck
36 * HighSpeed PLL uses PLL_REF_CLK for reference clck
441 else if (strcmp(hs_clock_type, "pll_ref_clk")) in dwc3_octeon_probe()
442 dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", in dwc3_octeon_probe()
449 if (strcmp(hs_clock_type, "pll_ref_clk")) in dwc3_octeon_probe()
450 dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", in dwc3_octeon_probe()
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| /linux/drivers/clk/ |
| H A D | clk-tps68470.c | 48 * PLL_REF_CLK should be as close as possible to 100kHz
49 * PLL_REF_CLK = input clk / XTALDIV[7:0] + 30)
51 * PLL_VCO_CLK = (PLL_REF_CLK * (plldiv*2 + 320))
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | cdns,dphy.yaml | 53 clocks = <&psm_clk>, <&pll_ref_clk>;
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | qcom,sdx75-tlmm.yaml | 78 pll_clk_aux, pll_ref_clk, pri_mi2s, prng_rosc, qdss_cti, qdss_gpio,
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| /linux/drivers/crypto/cavium/nitrox/ |
| H A D | nitrox_hal.c | 8 #define PLL_REF_CLK 50 macro
620 ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK; in nitrox_get_hwinfo()
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| /linux/drivers/phy/xilinx/ |
| H A D | phy-zynqmp.c | 186 * @pll_ref_clk: value to be written to register for corresponding ref clk rate
192 u8 pll_ref_clk; member
411 PLL_FREQ_MASK, ssc->pll_ref_clk); in xpsgtr_configure_pll()
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| /linux/drivers/gpu/drm/kmb/ |
| H A D | kmb_dsi.c | 870 /* pll_ref_clk: - valid range: 2~64 MHz; Typically 24 MHz in mipi_tx_pll_setup()
876 * -conditions: - (pll_ref_clk / N) >= 2 MHz in mipi_tx_pll_setup()
877 * -(pll_ref_clk / N) <= 8 MHz in mipi_tx_pll_setup()
881 * -Fvco = (M/N) * pll_ref_clk in mipi_tx_pll_setup()
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| /linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-sdx75.c | 874 MSM_PIN_FUNCTION(pll_ref_clk),
969 [37] = PINGROUP(37, qlink0_l_en, _, pll_ref_clk, prng_rosc, vsense_trigger_mirnat, _, _, _, _, _),
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| /linux/drivers/accel/habanalabs/goya/ |
| H A D | goya.c | 775 freq = PLL_REF_CLK; in goya_fetch_psoc_frequency()
777 freq = PLL_REF_CLK / (div_fctr + 1); in goya_fetch_psoc_frequency()
780 pll_clk = PLL_REF_CLK * (nf + 1) / in goya_fetch_psoc_frequency()
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| /linux/drivers/accel/habanalabs/gaudi/ |
| H A D | gaudi.c | 939 freq = PLL_REF_CLK; in gaudi_fetch_psoc_frequency()
941 freq = PLL_REF_CLK / (div_fctr + 1); in gaudi_fetch_psoc_frequency()
944 pll_clk = PLL_REF_CLK * (nf + 1) / in gaudi_fetch_psoc_frequency()
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| /linux/drivers/accel/habanalabs/common/ |
| H A D | habanalabs.h | 1328 #define PLL_REF_CLK 50 macro
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