| /linux/Documentation/devicetree/bindings/soc/xilinx/ |
| H A D | xlnx,vcu.txt | 16 - clocks: phandle for aclk and pll_ref clocksource
18 the axi clock. "pll_ref" is required for pll.
25 clock-names = "pll_ref", "aclk";
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| /linux/drivers/clk/samsung/ |
| H A D | clk-exynos-audss.c | 128 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
154 pll_ref = devm_clk_get(dev, "pll_ref"); in exynos_audss_clk_probe()
156 if (!IS_ERR(pll_ref)) in exynos_audss_clk_probe()
157 mout_audss_p[0] = __clk_get_name(pll_ref); in exynos_audss_clk_probe()
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| H A D | clk-s5pv210-audss.c | 70 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
106 pll_ref = devm_clk_get(&pdev->dev, "xxti"); in s5pv210_audss_clk_probe()
108 if (!IS_ERR(pll_ref)) in s5pv210_audss_clk_probe()
109 mout_audss_p[0] = __clk_get_name(pll_ref); in s5pv210_audss_clk_probe()
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | cdns,dphy.yaml | 29 - const: pll_ref
54 clock-names = "psm", "pll_ref";
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| H A D | mediatek,hdmi-phy.yaml | 42 - const: pll_ref
88 clock-names = "pll_ref";
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| /linux/drivers/clk/xilinx/ |
| H A D | xlnx_vcu.c | 52 * @pll_ref: pll ref clock source
62 struct clk *pll_ref; member
539 "vcu_pll", __clk_get_name(xvcu->pll_ref), in xvcu_register_clock_provider()
550 parent_data[0].fw_name = "pll_ref"; in xvcu_register_clock_provider()
662 xvcu->pll_ref = devm_clk_get(&pdev->dev, "pll_ref"); in xvcu_probe()
663 if (IS_ERR(xvcu->pll_ref)) { in xvcu_probe()
664 dev_err(&pdev->dev, "Could not get pll_ref clock\n"); in xvcu_probe()
665 return PTR_ERR(xvcu->pll_ref); in xvcu_probe()
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,exynos-audss-clock.yaml | 48 - const: pll_ref
79 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra-fixed.c | 80 /* pll_ref */ in tegra_osc_clk_init()
87 clk = clk_register_fixed_factor(NULL, "pll_ref", "osc", in tegra_osc_clk_init()
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| H A D | clk-tegra20.c | 466 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
663 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
668 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
692 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, in tegra20_pll_init()
868 /* pll_ref */ in tegra20_osc_clk_init()
870 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m", in tegra20_osc_clk_init()
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| H A D | clk-tegra124.c | 936 { .con_id = "pll_ref", .dt_id = TEGRA124_CLK_PLL_REF },
1092 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, in tegra124_pll_init()
1114 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra124_pll_init()
1120 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra124_pll_init()
1126 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, in tegra124_pll_init()
1148 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra124_pll_init()
1179 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra124_pll_init()
1191 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, in tegra124_pll_init()
1203 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref", in tegra124_pll_init()
1209 clk = tegra_clk_register_pllss("pll_c4", "pll_ref", clk_base, 0, in tegra124_pll_init()
[all …]
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| H A D | clk-tegra114.c | 810 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
905 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, in tegra114_pll_init()
919 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
924 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
929 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, in tegra114_pll_init()
947 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra114_pll_init()
973 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
983 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
993 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, in tegra114_pll_init()
1003 clk = tegra_clk_register_plle_tegra114("pll_e_out0", "pll_ref", in tegra114_pll_init()
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| H A D | clk-tegra-super-gen4.c | 233 clk = tegra_clk_register_pllc_tegra210("pll_x", "pll_ref", in tegra_super_clk_init()
237 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, in tegra_super_clk_init()
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| H A D | clk-tegra30.c | 593 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
811 static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
836 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
846 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, in tegra30_pll_init()
851 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
861 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
1369 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0, in tegra30_car_probe()
1379 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base, in tegra30_car_probe()
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| H A D | clk-tegra210.c | 2562 { .con_id = "pll_ref", .dt_id = TEGRA210_CLK_PLL_REF },
2627 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_ref" },
2628 { "pll_a1", &pll_a1_params, tegra_clk_pll_a1, "pll_ref" },
3200 clk = tegra_clk_register_pllc_tegra210("pll_c", "pll_ref", clk_base, in tegra210_pll_init()
3223 clk = tegra_clk_register_pllc_tegra210("pll_c2", "pll_ref", clk_base, in tegra210_pll_init()
3229 clk = tegra_clk_register_pllc_tegra210("pll_c3", "pll_ref", clk_base, in tegra210_pll_init()
3265 clk = clk_register_fixed_rate(NULL, "pll_u_vco", "pll_ref", 0, in tegra210_pll_init()
3322 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra210_pll_init()
3334 clk = tegra_clk_register_pllre_tegra210("pll_re_vco", "pll_ref", in tegra210_pll_init()
3357 clk = tegra_clk_register_plle_tegra210("pll_e", "pll_ref", in tegra210_pll_init()
[all …]
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| H A D | clk-tegra-periph.c | 503 "clk_m", "pll_re_out", "clk_32k", "pll_u_480M", "pll_c", "pll_ref"
806 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
807 GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
950 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, in init_pllp()
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| H A D | clk-pll.c | 1119 struct clk_hw *pll_ref = clk_hw_get_parent(hw); in clk_pllu_enable() local
1120 struct clk_hw *osc = clk_hw_get_parent(pll_ref); in clk_pllu_enable()
1851 /* ensure parent is set to pll_ref */ in _clk_plle_tegra_init_parent()
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| /linux/drivers/media/tuners/ |
| H A D | r820t.c | 547 u32 pll_ref; in r820t_set_pll() local
559 pll_ref = priv->cfg->xtal / 1000; in r820t_set_pll()
568 pll_ref /= 2; in r820t_set_pll()
574 pll_ref /= 2; in r820t_set_pll()
633 nint = vco_freq / (2 * pll_ref); in r820t_set_pll()
634 vco_fra = vco_freq - 2 * pll_ref * nint; in r820t_set_pll()
637 if (vco_fra < pll_ref / 64) { in r820t_set_pll()
639 } else if (vco_fra > pll_ref * 127 / 64) { in r820t_set_pll()
642 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) { in r820t_set_pll()
643 vco_fra = pll_ref * 127 / 128; in r820t_set_pll()
[all …]
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| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | qcom,sdx55-pinctrl.yaml | 72 nav_gpio, pa_indicator, pcie_clkreq, pci_e, pll_bist, pll_ref,
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| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-hdmi.c | 101 ref_clk = devm_clk_get(dev, "pll_ref"); in mtk_hdmi_phy_probe()
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| /linux/arch/arm/boot/dts/mediatek/ |
| H A D | mt7623n.dtsi | 268 clock-names = "pll_ref";
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos5410.dtsi | 87 clock-names = "pll_ref", "pll_in";
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| H A D | exynos4.dtsi | 73 clock-names = "pll_ref", "pll_in", "sclk_audio",
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| /linux/drivers/phy/cadence/ |
| H A D | cdns-dphy.c | 433 dphy->pll_ref_clk = devm_clk_get(&pdev->dev, "pll_ref"); in cdns_dphy_probe()
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| /linux/drivers/pinctrl/qcom/ |
| H A D | pinctrl-sdx55.c | 818 MSM_PIN_FUNCTION(pll_ref),
885 [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _),
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| H A D | pinctrl-sdx65.c | 750 MSM_PIN_FUNCTION(pll_ref),
819 [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _),
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