| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | nvidia,tegra234-xusb.yaml | 61 - const: pll_e
145 "pll_e";
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| H A D | nvidia,tegra186-xusb.yaml | 57 - const: pll_e
156 "pll_u_480m", "clk_m", "pll_e";
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| H A D | nvidia,tegra194-xusb.yaml | 57 - const: pll_e
160 "pll_e";
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| H A D | nvidia,tegra124-xusb.yaml | 71 - const: pll_e
183 "clk_m", "pll_e";
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | nvidia,tegra20-pcie.txt | 59 - pll_e
194 clock-names = "pex", "afi", "pll_e";
299 clock-names = "pex", "afi", "pll_e", "cml";
403 clock-names = "pex", "afi", "pll_e", "cml";
499 clock-names = "pex", "afi", "pll_e", "cml";
597 clock-names = "afi", "pex", "pll_e";
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| /linux/include/dt-bindings/clock/ |
| H A D | sunplus,sp7021-clkc.h | 77 #define PLL_E 65 macro
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| /linux/drivers/clk/ |
| H A D | clk-sp7021.c | 631 hws[PLL_E] = sp_pll_register(dev, "plle", &pd_ext, PLLE_CTL, in sp7021_clk_probe()
633 if (IS_ERR(hws[PLL_E])) in sp7021_clk_probe()
634 return PTR_ERR(hws[PLL_E]); in sp7021_clk_probe()
635 pd_e.hw = hws[PLL_E]; in sp7021_clk_probe()
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| /linux/drivers/pci/controller/ |
| H A D | pci-tegra.c | 336 struct clk *pll_e; member
1162 clk_disable_unprepare(pcie->pll_e); in tegra_pcie_power_off()
1220 err = clk_prepare_enable(pcie->pll_e); in tegra_pcie_power_on()
1268 pcie->pll_e = devm_clk_get(dev, "pll_e"); in tegra_pcie_clocks_get()
1269 if (IS_ERR(pcie->pll_e)) in tegra_pcie_clocks_get()
1270 return PTR_ERR(pcie->pll_e); in tegra_pcie_clocks_get()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra30.c | 557 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
1032 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1037 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1375 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base, in tegra30_car_probe()
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| H A D | clk-tegra124.c | 1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1203 clk = tegra_clk_register_plle_tegra114("pll_e", "pll_ref", in tegra124_pll_init()
1205 clk_register_clkdev(clk, "pll_e", NULL); in tegra124_pll_init()
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| H A D | clk-tegra20.c | 435 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
692 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, in tegra20_pll_init()
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| H A D | clk-tegra-periph.c | 447 "pll_p", "clk_m", "clk_32k", "pll_e"
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| H A D | clk-pll.c | 1868 WARN(1, "pll_e enabled with unsupported parent %s\n", in _clk_plle_tegra_init_parent()
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| /linux/arch/arm64/boot/dts/nvidia/ |
| H A D | tegra132.dtsi | 48 clock-names = "pex", "afi", "pll_e", "cml";
681 "pll_u_480m", "clk_m", "pll_e";
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| H A D | tegra210.dtsi | 47 clock-names = "pex", "afi", "pll_e", "cml";
1052 "pll_u_480m", "clk_m", "pll_e";
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| H A D | tegra186.dtsi | 1130 "pll_u_480m", "clk_m", "pll_e";
1371 clock-names = "pex", "afi", "pll_e";
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| H A D | tegra194.dtsi | 1311 "pll_e";
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| H A D | tegra234.dtsi | 3294 "pll_e";
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra124.dtsi | 53 clock-names = "pex", "afi", "pll_e", "cml";
760 "pll_u_480m", "clk_m", "pll_e";
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| H A D | tegra20.dtsi | 808 clock-names = "pex", "afi", "pll_e";
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| H A D | tegra30.dtsi | 53 clock-names = "pex", "afi", "pll_e", "cml";
|