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Searched full:pll_ctrl (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/clk/zynq/
H A Dpll.c17 * @pll_ctrl: PLL control register
25 void __iomem *pll_ctrl; member
83 fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
105 reg = readl(clk->pll_ctrl); in zynq_pll_is_enabled()
131 reg = readl(clk->pll_ctrl); in zynq_pll_enable()
133 writel(reg, clk->pll_ctrl); in zynq_pll_enable()
161 reg = readl(clk->pll_ctrl); in zynq_pll_disable()
163 writel(reg, clk->pll_ctrl); in zynq_pll_disable()
180 * @pll_ctrl: Pointer to PLL control register
187 void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, in clk_register_zynq_pll() argument
[all …]
/linux/drivers/clk/imx/
H A Dclk-fracn-gppll.c17 #define PLL_CTRL 0x0 macro
244 tmp = readl_relaxed(pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
246 writel_relaxed(tmp, pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
249 tmp = readl_relaxed(pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
251 writel_relaxed(tmp, pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
255 writel_relaxed(tmp, pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
259 writel_relaxed(tmp, pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
276 writel_relaxed(tmp, pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
277 readl(pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
286 writel_relaxed(tmp, pll->base + PLL_CTRL); in clk_fracn_gppll_set_rate()
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-usb.c20 PLL_CTRL, enumerator
28 [PLL_CTRL] = 0x18,
33 [PLL_CTRL] = 0x0c,
38 [PLL_CTRL] = 0x8,
139 bcm_usb_reg32_clrbits(regs + offset[PLL_CTRL], in bcm_usb_ss_phy_init()
141 bcm_usb_reg32_setbits(regs + offset[PLL_CTRL], in bcm_usb_ss_phy_init()
143 bcm_usb_reg32_setbits(regs + offset[PLL_CTRL], in bcm_usb_ss_phy_init()
149 ret = bcm_usb_pll_lock_check(regs + offset[PLL_CTRL], in bcm_usb_ss_phy_init()
163 bcm_usb_reg32_clrbits(regs + offset[PLL_CTRL], in bcm_usb_hs_phy_init()
165 bcm_usb_reg32_setbits(regs + offset[PLL_CTRL], in bcm_usb_hs_phy_init()
[all …]
/linux/sound/soc/codecs/
H A Dda7213.c903 u8 pll_ctrl, pll_status; in da7213_dai_event() local
920 pll_ctrl = snd_soc_component_read(component, DA7213_PLL_CTRL); in da7213_dai_event()
921 if (!(pll_ctrl & DA7213_PLL_SRM_EN)) in da7213_dai_event()
925 if (pll_ctrl & DA7213_PLL_32K_MODE) { in da7213_dai_event()
948 pll_ctrl = snd_soc_component_read(component, DA7213_PLL_CTRL); in da7213_dai_event()
949 if (pll_ctrl & DA7213_PLL_32K_MODE) { in da7213_dai_event()
1608 u8 pll_ctrl, indiv_bits, indiv; in _da7213_set_component_pll() local
1654 pll_ctrl = indiv_bits; in _da7213_set_component_pll()
1661 DA7213_PLL_MODE_MASK, pll_ctrl); in _da7213_set_component_pll()
1666 pll_ctrl | in _da7213_set_component_pll()
[all...]
H A Dda7219.c803 u8 pll_ctrl, pll_status; in da7219_dai_event() local
831 pll_ctrl = snd_soc_component_read(component, DA7219_PLL_CTRL); in da7219_dai_event()
832 if ((pll_ctrl & DA7219_PLL_MODE_MASK) != DA7219_PLL_MODE_SRM) in da7219_dai_event()
1224 u8 pll_ctrl, indiv_bits, indiv; in da7219_set_pll() local
1255 pll_ctrl = indiv_bits; in da7219_set_pll()
1260 pll_ctrl |= DA7219_PLL_MODE_BYPASS; in da7219_set_pll()
1263 DA7219_PLL_MODE_MASK, pll_ctrl); in da7219_set_pll()
1266 pll_ctrl |= DA7219_PLL_MODE_NORMAL; in da7219_set_pll()
1269 pll_ctrl |= DA7219_PLL_MODE_SRM; in da7219_set_pll()
1289 pll_ctrl); in da7219_set_pll()
H A Dda7219-aad.c116 u8 pll_srm_sts, pll_ctrl, gain_ramp_ctrl, accdet_cfg8; in da7219_aad_hptest_work() local
147 pll_ctrl = snd_soc_component_read(component, DA7219_PLL_CTRL); in da7219_aad_hptest_work()
148 if ((pll_ctrl & DA7219_PLL_MODE_MASK) == DA7219_PLL_MODE_BYPASS) in da7219_aad_hptest_work()
316 ((pll_ctrl & DA7219_PLL_MODE_MASK) == DA7219_PLL_MODE_BYPASS)) in da7219_aad_hptest_work()
H A Dda7218.c1399 u8 pll_ctrl, pll_status, refosc_cal; in da7218_dai_event() local
1441 pll_ctrl = snd_soc_component_read(component, DA7218_PLL_CTRL); in da7218_dai_event()
1442 if ((pll_ctrl & DA7218_PLL_MODE_MASK) != DA7218_PLL_MODE_SRM) in da7218_dai_event()
1861 u8 pll_ctrl, indiv_bits, indiv; in da7218_set_dai_pll() local
1892 pll_ctrl = indiv_bits; in da7218_set_dai_pll()
1897 pll_ctrl |= DA7218_PLL_MODE_BYPASS; in da7218_set_dai_pll()
1900 DA7218_PLL_MODE_MASK, pll_ctrl); in da7218_set_dai_pll()
1903 pll_ctrl |= DA7218_PLL_MODE_NORMAL; in da7218_set_dai_pll()
1906 pll_ctrl |= DA7218_PLL_MODE_SRM; in da7218_set_dai_pll()
1926 pll_ctrl); in da7218_set_dai_pll()
[all...]
H A Dsma1303.h414 /* PLL_CTRL : 0x8E */
/linux/include/linux/clk/
H A Dzynq.h15 void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c716 const struct iproc_pll_ctrl *pll_ctrl, in iproc_pll_clk_setup() argument
731 if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) in iproc_pll_clk_setup()
755 if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { in iproc_pll_clk_setup()
761 if (pll_ctrl->flags & IPROC_CLK_PLL_SPLIT_STAT_CTRL) { in iproc_pll_clk_setup()
772 pll->ctrl = pll_ctrl; in iproc_pll_clk_setup()
H A Dclk-iproc.h204 const struct iproc_pll_ctrl *pll_ctrl,
/linux/arch/m68k/q40/
H A Dconfig.c248 pll->pll_ctrl = 0; in q40_get_rtc_pll()
263 if (!pll->pll_ctrl) { in q40_set_rtc_pll()
/linux/drivers/media/dvb-frontends/
H A Ddib3000.h37 int (*tuner_pass_ctrl)(struct dvb_frontend *fe, int onoff, u8 pll_ctrl);
/linux/include/uapi/linux/
H A Drtc.h61 int pll_ctrl; /* placeholder for fancier control */ member
/linux/drivers/video/fbdev/
H A Dsstfb.c1027 u8 pll_ctrl; in sst_set_pll_ics() local
1030 pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA); in sst_set_pll_ics()
1039 (pll_ctrl & 0xd8) in sst_set_pll_ics()
1050 (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A); in sst_set_pll_ics()
/linux/drivers/media/pci/cx23885/
H A Dcx23885-reg.h140 #define PLL_CTRL 0x00000494 macro
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-reg.h121 #define PLL_CTRL 0x104C macro
/linux/drivers/clk/ti/
H A Dfapll.c15 /* FAPLL Control Register PLL_CTRL */
/linux/drivers/phy/ti/
H A Dphy-ti-pipe3.c784 devm_platform_ioremap_resource_byname(pdev, "pll_ctrl"); in ti_pipe3_get_pll_base()
/linux/include/linux/mfd/
H A Dtps6594.h701 /* PLL_CTRL register field definition */
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800.h229 #define PLL_CTRL 0x0050 macro
H A Drt2800lib.c5916 reg = rt2800_register_read(rt2x00dev, PLL_CTRL); in rt2800_init_registers()
5918 rt2800_register_write(rt2x00dev, PLL_CTRL, reg); in rt2800_init_registers()
/linux/drivers/media/usb/cx231xx/
H A Dcx231xx-reg.h646 #define PLL_CTRL 0x494 macro
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c2085 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */ in xgbe_phy_pll_ctrl()