| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | allwinner,sun4i-a10-pll3-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
20 const: allwinner,sun4i-a10-pll3-clk
44 compatible = "allwinner,sun4i-a10-pll3-clk";
47 clock-output-names = "pll3";
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| H A D | renesas,sh73a0-cpg-clocks.txt | 19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
32 "pll3", "dsi0phy", "dsi1phy",
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| H A D | allwinner,sun4i-a10-tcon-ch0-clk.yaml | 64 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
73 clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
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| H A D | allwinner,sun9i-a80-cpus-clk.yaml | 48 clocks = <&osc32k>, <&osc24M>, <&pll4>, <&pll3>;
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| H A D | allwinner,sun4i-a10-display-clk.yaml | 53 clocks = <&pll3>, <&pll7>, <&pll5 1>;
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| H A D | prima2-clock.txt | 19 pll3 4
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| H A D | renesas,cpg-clocks.yaml | 207 - const: pll3
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| H A D | st,stm32mp25-rcc.yaml | 114 - description: CK_SCMI_PLL3 PLL3 clock
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| H A D | qcom,mmcc.yaml | 94 - const: pll3
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| /freebsd/sys/arm/freescale/vybrid/ |
| H A D | vf_anadig.c | 55 #define ANADIG_PLL3_CTRL 0x010 /* PLL3 Control */
68 #define ANADIG_PLL3_PFD 0x0F0 /* PLL3 PFD */
|
| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stm32mp151c-mecio1r0.dts | 46 assigned-clock-rates = <125000000>; /* Clock PLL3 to 625Mhz in tf-a. */
|
| /freebsd/sys/contrib/device-tree/src/arm/qcom/ |
| H A D | qcom-msm8960.dtsi | 168 <&gcc PLL3>,
176 "pll3",
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| H A D | qcom-apq8064.dtsi | 734 <&gcc PLL3>,
742 "pll3",
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| /freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
| H A D | stm32mp13-clks.h | 21 #define PLL3 8 macro
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| H A D | qcom,gcc-ipq806x.h | 231 #define PLL3 222 macro
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| H A D | stm32mp1-clks.h | 185 #define PLL3 178 macro
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| H A D | qcom,gcc-mdm9615.h | 288 #define PLL3 278 macro
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| H A D | qcom,gcc-msm8960.h | 286 #define PLL3 278 macro
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| H A D | tegra234-clock.h | 238 /** @brief Logical clk for setting the UPHY PLL3 rate */
|
| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_attach.c | 3373 #define PLL3 0x16188 macro
3382 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) & ~(PLL3_DO_MEAS_MASK))); in ar9300_get_pll3_sqsum_dvc()
3384 OS_REG_WRITE(ah, PLL3, (OS_REG_READ(ah, PLL3) | PLL3_DO_MEAS_MASK)); in ar9300_get_pll3_sqsum_dvc()
3390 return (( OS_REG_READ(ah, PLL3) & SQSUM_DVC_MASK ) >> 3); in ar9300_get_pll3_sqsum_dvc()
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| H A D | ar9300_reset.c | 1415 /* Rewrite DDR PLL2 and PLL3 */ in ar9300_init_pll()
1443 /* Rewrite DDR PLL2 and PLL3 */ in ar9300_init_pll()
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| /freebsd/sys/dev/clk/allwinner/ |
| H A D | ccu_a13.c | 188 /* Missing PLL3-Video */
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| /freebsd/sys/contrib/device-tree/src/arm/renesas/ |
| H A D | sh73a0.dtsi | 652 "pll3", "dsi0phy", "dsi1phy",
|