Searched full:pll1_refclk (Results 1 – 4 of 4) sorted by relevance
39 PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).40 pll1_refclk is optional and used for multi-protocol configurations requiring42 Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.50 - enum: [ pll1_refclk, phy_en_refclk ]
71 PLL1_REFCLK, enumerator588 wiz->mux_sel_field[PLL1_REFCLK] = in wiz_regfield_init()590 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) { in wiz_regfield_init()592 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]); in wiz_regfield_init()
304 #define PLL1_REFCLK_NAME "pll1_refclk"
2815 cdns_phy->clk1 = devm_clk_get_optional(cdns_phy->dev, "pll1_refclk"); in cdns_torrent_of_get_clk()