Searched full:pll0_auxclk (Results 1 – 6 of 6) sorted by relevance
117 davinci_pll_auxclk_register(dev, "pll0_auxclk", base); in da850_pll0_init()119 clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk", in da850_pll0_init()
508 const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" }; in da8xx_cfgchip_register_usb0_clk48()619 * All existing boards use pll0_auxclk as the parent and new boards in da8xx_cfgchip_register_usb_phy_clk()
147 pll0_auxclk: auxclk { label391 <&pll0_auxclk>;498 clocks = <&pll0_auxclk>;508 clocks = <&pll0_auxclk>;526 clocks = <&pll0_auxclk>;531 clocks = <&pll0_auxclk>;
65 clocks = <&pll0_auxclk>;
71 pll0_auxclk: auxclk {
62 clocks = <&psc1 1>, <&usb_refclkin>, <&pll0_auxclk>;