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/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
39 - fsl,p3041-clockgen
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/linux/arch/arm/boot/dts/st/
H A Dstih410-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih410-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
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H A Dstih418-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih418-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
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/linux/drivers/clk/
H A Dclk-npcm8xx.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/clk-provider.h>
23 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
24 #include <soc/nuvoton/clock-npcm8xx.h>
91 { "pll0", { .index = 0 }, NPCM8XX_PLLCON0, 0 },
190 { NPCM8XX_CLKDIV1, 21, 5, "pre_adc", &npcm8xx_muxes[6].hw, CLK_DIVIDER_READ_ONLY, 0, -1 },
237 val = readl_relaxed(pll->pllcon); in npcm8xx_clk_pll_recalc_rate()
265 return ERR_PTR(-ENOMEM); in npcm8xx_clk_register_pll()
273 pll->pllcon = pllcon; in npcm8xx_clk_register_pll()
274 pll->hw.init = &init; in npcm8xx_clk_register_pll()
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H A Dclk-npcm7xx.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
51 val = readl_relaxed(pll->pllcon); in npcm7xx_clk_pll_recalc_rate()
79 return ERR_PTR(-ENOMEM); in npcm7xx_clk_register_pll()
89 pll->pllcon = pllcon; in npcm7xx_clk_register_pll()
90 pll->hw.init = &init; in npcm7xx_clk_register_pll()
92 hw = &pll->hw; in npcm7xx_clk_register_pll()
142 * defined in include/dt-bindings/clock/nuvoton, NPCM7XX-clock.h for
143 * this specific clock. Otherwise, set to -1.
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