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/linux/drivers/clk/spear/
H A Dclk-vco-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * VCO-PLL clock implementation
9 #define pr_fmt(fmt) "clk-vco-pll: " fmt
11 #include <linux/clk-provider.h>
18 * DOC: VCO-PLL clock
20 * VCO and PLL rate are derived from following equations:
23 * vco = (2 * M[15:8] * Fin)/N
26 * vco = (2 * M[15:0] * Fin)/(256 * N)
28 * pll_rate = pll/2^p
30 * vco and pll are very closely bound to each other, "vco needs to program:
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
25 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
42 - silabs,si5340
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/linux/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
36 #define ACCR_XPDIS (1 << 31) /* Core PLL Output Disable */
37 #define ACCR_SPDIS (1 << 30) /* System PLL Output Disable */
45 #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
47 #define ACCR_XN_MASK (0x7 << 8) /* Core PLL Turbo-Mode-to-Run-Mode Ratio */
48 #define ACCR_XL_MASK (0x1f) /* Core PLL Run-Mode-to-Oscillator Ratio */
77 .hss = HSS_##_hss##M, \
78 .dmcfs = DMCFS_##_dmc##M, \
79 .smcfs = SMCFS_##_smc##M, \
80 .sflfs = SFLFS_##_sfl##M, \
[all …]
/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
[all …]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_output_7a2000.c1 // SPDX-License-Identifier: GPL-2.0+
18 * Display pipe 0 is attached with a built-in transparent VGA encoder and
19 * a built-in HDMI encoder.
20 * Display pipe 1 has only one built-in HDMI encoder connected.
22 * | +-----+ | | |
23 * | CRTC0 -+--> | VGA | ----> VGA Connector ---> | VGA Monitor |<---+
24 * | | +-----+ | |_____________| |
26 * | | +------+ | | | |
27 * | +--> | HDMI | ----> HDMI Connector --> | HDMI Monitor |<--+
28 * | +------+ | |______________| |
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu-sun5i.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun5i.h"
30 .m = _SUNXI_CCU_DIV(0, 2),
34 .hw.init = CLK_HW_INIT("pll-core",
42 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44 * pll audio).
46 * With sigma-delta modulation for fractional-N on the audio PLL,
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
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H A Dccu-suniv-f1c100s.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include "ccu-suniv-f1c100s.h"
33 .m = _SUNXI_CCU_DIV(0, 2),
39 .hw.init = CLK_HW_INIT("pll-cpu", "osc24M",
46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * pll audio).
55 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
58 0, 5, /* M */
63 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
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H A Dccu-sun8i-h3.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
26 #include "ccu-sun8i-h3.h"
28 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
32 0, 2, /* M */
39 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
41 * pll audio).
43 * With sigma-delta modulation for fractional-N on the audio PLL,
53 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
54 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
[all …]
H A Dccu-sun4i-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
28 #include "ccu-sun4i-a10.h"
34 .m = _SUNXI_CCU_DIV(0, 2),
38 .hw.init = CLK_HW_INIT("pll-core",
46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * pll audio).
50 * With sigma-delta modulation for fractional-N on the audio PLL,
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
[all …]
H A Dccu-sun55i-a523-mcu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
6 * Copyright (C) 2023-2024 Arm Ltd.
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
15 #include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
31 { .fw_name = "r-ahb" }
35 { .fw_name = "r-apb0" }
40 { .rate = 2167603200, .pattern = 0xa000a234, .m = 1, .n = 90 }, /* div2->22.5792 */
41 { .rate = 2359296000, .pattern = 0xa0009ba6, .m = 1, .n = 98 }, /* div2->24.576 */
[all …]
H A Dccu-sun8i-a23.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
25 #include "ccu-sun8i-a23-a33.h"
34 .m = _SUNXI_CCU_DIV(0, 2),
39 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
46 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
48 * pll audio).
50 * With sigma-delta modulation for fractional-N on the audio PLL,
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
[all …]
H A Dccu-sun8i-a33.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-a23-a33.h"
32 .m = _SUNXI_CCU_DIV(0, 2),
37 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
46 * pll audio).
48 * With sigma-delta modulation for fractional-N on the audio PLL,
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
[all …]
H A Dccu-sun50i-a100.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-a100.h"
34 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
39 * The M factor is present in the register's description, but not in the
40 * frequency formula, and it's documented as "M is only used for backdoor
50 .hw.init = CLK_HW_INIT("pll-cpux", "dcxo24M",
62 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
66 .hw.init = CLK_HW_INIT("pll-ddr0", "dcxo24M",
78 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
[all …]
H A Dccu-sun8i-a83t.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
22 #include "ccu-sun8i-a83t.h"
29 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
44 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
65 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
66 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
74 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
[all …]
H A Dccu-sun50i-a64.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun50i-a64.h"
31 .m = _SUNXI_CCU_DIV(0, 2),
35 .hw.init = CLK_HW_INIT("pll-cpux",
43 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
45 * pll audio).
47 * With sigma-delta modulation for fractional-N on the audio PLL,
57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
[all …]
H A Dccu-sun50i-h6.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
23 #include "ccu-sun50i-h6.h"
26 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
31 * The M factor is present in the register's description, but not in the
32 * frequency formula, and it's documented as "M is only used for backdoor
42 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
54 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
69 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
[all …]
H A Dccu-sun50i-h616.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
25 #include "ccu-sun50i-h616.h"
28 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
33 * The M factor is present in the register's description, but not in the
34 * frequency formula, and it's documented as "M is only used for backdoor
44 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
56 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
60 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
71 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
[all …]
/linux/drivers/clk/
H A Dclk-si5341.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/clk-provider.h>
46 /* There is one PLL running at 13500–14256 MHz */
50 /* The 5 frequency synthesizers obtain their input from the PLL */
127 /* Input dividers (48-bit) */
132 /* PLL configuration */
138 ((output)->data->reg_output_offset[(output)->index])
143 ((output)->data->reg_rdiv_offset[(output)->index])
220 * using only the XTAL input, without pre-divider.
364 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
[all …]
H A Dclk-sp7021.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
7 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sunplus,sp7021-clkc.h>
142 /* valid m values: 27M must be divisible by m */ in plltv_integer_div()
146 u32 m, n, r; in plltv_integer_div() local
160 for (m = 0; m < ARRAY_SIZE(m_table); m++) { in plltv_integer_div()
161 nf = fvco * m_table[m]; in plltv_integer_div()
166 if (m >= ARRAY_SIZE(m_table)) { in plltv_integer_div()
167 ret = -EINVAL; in plltv_integer_div()
172 clk->p[SEL_FRA] = 0; in plltv_integer_div()
[all …]
/linux/drivers/clk/ralink/
H A Dclk-mt7621.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
16 #include <dt-bindings/clock/mt7621-clk.h>
17 #include <dt-bindings/reset/mt7621-reset.h>
71 GATE(MT7621_CLK_HSDMA, "hsdma", "150m", BIT(5)),
72 GATE(MT7621_CLK_FE, "fe", "250m", BIT(6)),
73 GATE(MT7621_CLK_SP_DIVTX, "sp_divtx", "270m", BIT(7)),
74 GATE(MT7621_CLK_TIMER, "timer", "50m", BIT(8)),
75 GATE(MT7621_CLK_PCM, "pcm", "270m", BIT(11)),
[all …]
/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
101 /* Radeon Xpress 200m */
115 /* IGP330M/340M/350M (U2) */
263 static int default_dynclk = -2;
283 if (rinfo->no_schedule || oops_in_progress) in _radeon_msleep()
291 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ in radeon_pll_errata_after_index_slow()
298 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { in radeon_pll_errata_after_data_slow()
302 if (rinfo->errata & CHIP_ERRATA_R300_CG) { in radeon_pll_errata_after_data_slow()
317 spin_lock_irqsave(&rinfo->reg_lock, flags); in _OUTREGP()
322 spin_unlock_irqrestore(&rinfo->reg_lock, flags); in _OUTREGP()
[all …]
H A Dradeonfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/i2c-algo-bit.h>
45 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
62 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
63 ((rinfo)->family == CHIP_FAMILY_RV200) || \
64 ((rinfo)->family == CHIP_FAMILY_RS100) || \
65 ((rinfo)->family == CHIP_FAMILY_RS200) || \
66 ((rinfo)->family == CHIP_FAMILY_RV250) || \
67 ((rinfo)->family == CHIP_FAMILY_RV280) || \
68 ((rinfo)->family == CHIP_FAMILY_RS300))
[all …]
/linux/drivers/clk/qcom/
H A Dclk-rcg2.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk-provider.h>
23 #include "clk-rcg.h"
49 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
50 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
51 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
52 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
73 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in clk_rcg2_is_enabled()
90 if (cfg == rcg->parent_map[i].cfg) in __clk_rcg2_get_parent()
104 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_get_parent()
[all …]
/linux/drivers/crypto/
H A Dhifn_795x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
16 #include <linux/dma-mapping.h>
30 "PLL reference clock (pci[freq] or ext[freq], default ext)");
108 #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
109 #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
110 #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
111 #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
112 #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
113 #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
177 #define HIFN_1_PLL 0x4c /* 795x: PLL config */
[all …]
/linux/drivers/clk/meson/
H A Da1-pll.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
13 #include "clk-pll.h"
14 #include "clk-regmap.h"
15 #include "meson-clkc-utils.h"
27 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
36 .m = {
107 .m = {
182 * b) CCF has a clock hand-off mechanism to make the sure the
301 .num = ARRAY_SIZE(a1_pll_hw_clks),
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