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/linux/drivers/clk/spear/
H A Dclk-vco-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * VCO-PLL clock implementation
9 #define pr_fmt(fmt) "clk-vco-pll: " fmt
11 #include <linux/clk-provider.h>
18 * DOC: VCO-PLL clock
20 * VCO and PLL rate are derived from following equations:
23 * vco = (2 * M[15:8] * Fin)/N
26 * vco = (2 * M[15:0] * Fin)/(256 * N)
28 * pll_rate = pll/2^p
30 * vco and pll are very closely bound to each other, "vco needs to program:
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/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
25 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
42 - silabs,si5340
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/linux/drivers/clk/qcom/
H A Dclk-rcg2.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/clk-provider.h>
23 #include "clk-rcg.h"
49 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
50 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
51 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
52 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
73 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); in clk_rcg2_is_enabled()
90 if (cfg == rcg->parent_map[i].cfg) in __clk_rcg2_get_parent()
104 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); in clk_rcg2_get_parent()
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/linux/drivers/video/fbdev/aty/
H A Dradeonfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/i2c-algo-bit.h>
45 CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
62 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
63 ((rinfo)->family == CHIP_FAMILY_RV200) || \
64 ((rinfo)->family == CHIP_FAMILY_RS100) || \
65 ((rinfo)->family == CHIP_FAMILY_RS200) || \
66 ((rinfo)->family == CHIP_FAMILY_RV250) || \
67 ((rinfo)->family == CHIP_FAMILY_RV280) || \
68 ((rinfo)->family == CHIP_FAMILY_RS300))
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H A Dradeon_base.c38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
101 /* Radeon Xpress 200m */
115 /* IGP330M/340M/350M (U2) */
263 static int default_dynclk = -2;
283 if (rinfo->no_schedule || oops_in_progress) in _radeon_msleep()
291 /* Called if (rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS) is set */ in radeon_pll_errata_after_index_slow()
298 if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) { in radeon_pll_errata_after_data_slow()
302 if (rinfo->errata & CHIP_ERRATA_R300_CG) { in radeon_pll_errata_after_data_slow()
317 spin_lock_irqsave(&rinfo->reg_lock, flags); in _OUTREGP()
322 spin_unlock_irqrestore(&rinfo->reg_lock, flags); in _OUTREGP()
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/linux/drivers/video/fbdev/matrox/
H A Dmatroxfb_maven.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
71 0, WLMAX - BLMIN, 1, 379 - BLMIN,
91 0, ARRAY_SIZE(maven_gamma) - 1, 1, 3,
110 -EINVAL: id not found, return failure
111 -ENOENT: id not found, create fake disabled control */
118 return -EINVAL; in get_ctrl_id()
120 return -ENOENT; in get_ctrl_id()
126 return -EINVAL; in get_ctrl_id()
136 return (int*)((char*)(md->primary_head) + maven_controls[idx].control); in get_ctrl_ptr()
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/linux/include/linux/
H A Djiffies.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 * The following defines establish the engineering parameters of the PLL
47 /* Suppose we want to divide two numbers NOM and DEN: NOM/DEN, then we can
49 * (NOM << LSH) / DEN
53 * - (NOM / DEN) fits in (32 - LSH) bits.
54 * - (NOM % DEN) fits in (32 - LSH) bits.
56 #define SH_DIV(NOM,DEN,LSH) ( (((NOM) / (DEN)) << (LSH)) \ argument
57 + ((((NOM) % (DEN)) << (LSH)) + (DEN) / 2) / (DEN))
75 * The 64-bit value is not atomic on 32-bit systems - you MUST NOT read it
79 * jiffies and jiffies_64 are at the same address for little-endian systems
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/linux/drivers/clk/
H A Dclk-si5341.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/clk-provider.h>
46 /* There is one PLL running at 13500–14256 MHz */
50 /* The 5 frequency synthesizers obtain their input from the PLL */
127 /* Input dividers (48-bit) */
132 /* PLL configuration */
138 ((output)->data->reg_output_offset[(output)->index])
143 ((output)->data->reg_rdiv_offset[(output)->index])
220 * using only the XTAL input, without pre-divider.
364 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
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/linux/sound/pci/
H A Dsonicvibes.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include <linux/dma-mapping.h>
37 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
61 #define SV_REG(sonic, x) ((sonic)->enh_port + SV_REG_##x)
64 #define SV_ENHANCED 0x01 /* audio mode select - enhanced mode */
68 #define SV_INTA 0x20 /* INTA driving - shoul
472 unsigned int r, m = 0, n = 0; snd_sonicvibes_pll() local
510 unsigned int r, m, n; snd_sonicvibes_setpll() local
545 unsigned int rate, div, r, m, n; snd_sonicvibes_hw_constraint_dac_rate() local
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 Copyright (c) 2008 Michael Buesch <m@bues.ch>
8 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
96 enum nl80211_band band = b43_current_band(dev->wl); in b43_nphy_ipa()
97 return ((dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) || in b43_nphy_ipa()
98 (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ)); in b43_nphy_ipa()
101 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
112 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
137 b43err(dev->wl, "RF sequence status timeout\n"); in b43_nphy_force_rf_sequence()
149 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
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