Home
last modified time | relevance | path

Searched +full:platform +full:- +full:pll (Results 1 – 25 of 74) sorted by relevance

123

/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqoriq-clock.txt5 multiple phase locked loops (PLL) to create a variety of frequencies
14 --------------- -------------
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
28 * "fsl,p4080-clockgen"
29 * "fsl,p5020-clockgen"
30 * "fsl,p5040-clockgen"
[all …]
H A Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 multiple phase locked loops (PLL) to create a variety of frequencies
24 --------------- -------------
36 - items:
37 - enum:
38 - fsl,p2041-clockgen
[all …]
H A Dfsl,qoriq-clock-legacy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
24 - fsl,qoriq-core-mux-1.0
25 - fsl,qoriq-core-mux-2.0
[all …]
H A Daltr_socfpga.txt1 Device Tree Clock bindings for Altera's SoCFPGA platform
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
17 either an oscillator or a pll output.
[all …]
H A Dcalxeda.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda highbank platform Clock Controller
13 "hb-sregs" node.
16 - Andre Przywara <andre.przywara@arm.com>
19 "#clock-cells":
24 - calxeda,hb-pll-clock
25 - calxeda,hb-a9periph-clock
26 - calxeda,hb-a9bus-clock
[all …]
H A Dfsl,flexspi-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,flexspi-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
14 derived from the platform PLL.
19 - fsl,ls1028a-flexspi-clk
20 - fsl,lx2160a-flexspi-clk
28 '#clock-cells':
31 clock-output-names:
[all …]
H A Dmicrochip,pic32.txt2 ----------------------------------------
3 Microchip clock controller is consists of few oscillators, PLL, multiplexer
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible: shall be "microchip,pic32mzda-clk".
11 - reg: shall contain base address and length of clock registers.
12 - #clock-cells: shall be 1.
15 - microchip,pic32mzda-sosc: shall be added only if platform has
19 rootclk: clock-controller@1f801200 {
20 compatible = "microchip,pic32mzda-clk";
22 #clock-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/
H A Dqman.txt3 Copyright (C) 2008 - 2014 Freescale Semiconductor Inc.
7 - QMan Node
8 - QMan Private Memory Nodes
9 - Example
13 The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan
16 flow-level queuing, is also responsible for congestion management functions such
22 - compatible
26 May include "fsl,<SoC>-qman"
28 - reg
30 Value type: <prop-encoded-array>
[all …]
/freebsd/sys/contrib/device-tree/src/arm/vt8500/
H A Dwm8850.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
[all …]
H A Dwm8750.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8750.dtsi - Device tree file for Wondermedia WM8750 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <0>;
15 #size-cells = <0>;
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "simple-bus";
44 interrupt-parent = <&intc0>;
[all …]
H A Dwm8650.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8650.dtsi - Device tree file for Wondermedia WM8650 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <0>;
15 #size-cells = <0>;
19 compatible = "arm,arm926ej-s";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "simple-bus";
[all …]
H A Dwm8505.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * wm8505.dtsi - Device tree file for Wondermedia WM8505 SoC
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <0>;
15 #size-cells = <0>;
19 compatible = "arm,arm926ej-s";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 compatible = "simple-bus";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,edp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,edp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
14 The Qualcomm eDP PHY is found in a number of Qualcomm platform and provides
20 - qcom,sc7280-edp-phy
21 - qcom,sc8180x-edp-phy
22 - qcom,sc8280xp-dp-phy
23 - qcom,sc8280xp-edp-phy
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm850-samsung-w737.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
11 #include <dt-bindings/input/gpio-keys.h>
12 #include <dt-binding
[all...]
H A Dsc8280xp-lenovo-thinkpad-x13s.dts1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
9 #include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/gpio-keys.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
17 #include "sc8280xp-pmics.dtsi"
21 compatible = "lenovo,thinkpad-x13s", "qcom,sc8280xp";
[all …]
H A Dsm8250-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/sound/qcom,q6afe.h>
10 #include <dt-bindings/sound/qcom,q6asm.h>
11 #include <dt-bindings/gpio/gpio.h>
20 compatible = "qcom,sm8250-mtp", "qcom,sm8250";
21 chassis-type = "handset";
27 wcd938x: audio-codec {
28 compatible = "qcom,wcd9380-codec";
[all …]
H A Dsdm850-lenovo-yoga-c630.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/qcom,q6afe.h>
14 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm845-wcd9340.dtsi"
24 /delete-node/ &ipa_fw_mem;
25 /delete-node/ &ipa_gsi_mem;
[all …]
H A Dx1e80100-qcp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
12 #include "x1e80100-pmics.dtsi"
16 compatible = "qcom,x1e80100-qcp", "qcom,x1e80100";
22 wcd938x: audio-codec {
23 compatible = "qcom,wcd9385-codec";
25 pinctrl-names = "default";
26 pinctrl-0 = <&wcd_default>;
[all …]
H A Dx1e80100-crd.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/gpio-keys.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 #include "x1e80100-pmics.dtsi"
18 compatible = "qcom,x1e80100-crd", "qcom,x1e80100";
24 wcd938x: audio-codec {
25 compatible = "qcom,wcd9385-codec";
[all …]
H A Dsdm845-db845c.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
11 #include <dt-bindings/sound/qcom,q6afe.h>
12 #include <dt-bindings/sound/qcom,q6asm.h>
14 #include "sdm845-wcd9340.dtsi"
21 qcom,msm-id = <341 0x20001>;
22 qcom,board-id = <8 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arc/
H A Daxc003_idu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <33333333>;
[all …]
H A Daxc003.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
14 #address-cells = <2>;
15 #size-cells = <2>;
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
24 input_clk: input-clk {
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
[all …]
H A Daxs10x_mb.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/amlogic,g12-ddr-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiucheng Xu <jiucheng.xu@amlogic.com>
15 The bandwidth is counted in the timer ISR. Different platform
21 - amlogic,g12a-ddr-pmu
22 - amlogic,g12b-ddr-pmu
23 - amlogic,sm1-ddr-pmu
27 - description: DMC bandwidth register space.
[all …]

123