xref: /freebsd/sys/contrib/device-tree/Bindings/display/msm/dsi-controller-main.yaml (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0)
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Display DSI controller
8
9maintainers:
10  - Krishna Manikandan <quic_mkrishn@quicinc.com>
11
12properties:
13  compatible:
14    oneOf:
15      - items:
16          - enum:
17              - qcom,apq8064-dsi-ctrl
18              - qcom,msm8226-dsi-ctrl
19              - qcom,msm8916-dsi-ctrl
20              - qcom,msm8953-dsi-ctrl
21              - qcom,msm8974-dsi-ctrl
22              - qcom,msm8996-dsi-ctrl
23              - qcom,msm8998-dsi-ctrl
24              - qcom,qcm2290-dsi-ctrl
25              - qcom,sc7180-dsi-ctrl
26              - qcom,sc7280-dsi-ctrl
27              - qcom,sdm660-dsi-ctrl
28              - qcom,sdm670-dsi-ctrl
29              - qcom,sdm845-dsi-ctrl
30              - qcom,sm6115-dsi-ctrl
31              - qcom,sm6125-dsi-ctrl
32              - qcom,sm6350-dsi-ctrl
33              - qcom,sm6375-dsi-ctrl
34              - qcom,sm8150-dsi-ctrl
35              - qcom,sm8250-dsi-ctrl
36              - qcom,sm8350-dsi-ctrl
37              - qcom,sm8450-dsi-ctrl
38              - qcom,sm8550-dsi-ctrl
39              - qcom,sm8650-dsi-ctrl
40          - const: qcom,mdss-dsi-ctrl
41      - enum:
42          - qcom,dsi-ctrl-6g-qcm2290
43          - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
44        deprecated: true
45
46  reg:
47    maxItems: 1
48
49  reg-names:
50    const: dsi_ctrl
51
52  interrupts:
53    maxItems: 1
54
55  clocks:
56    description: |
57      Several clocks are used, depending on the variant. Typical ones are::
58       - bus:: Display AHB clock.
59       - byte:: Display byte clock.
60       - byte_intf:: Display byte interface clock.
61       - core:: Display core clock.
62       - core_mss:: Core MultiMedia SubSystem clock.
63       - iface:: Display AXI clock.
64       - mdp_core:: MDP Core clock.
65       - mnoc:: MNOC clock
66       - pixel:: Display pixel clock.
67    minItems: 3
68    maxItems: 9
69
70  clock-names:
71    minItems: 3
72    maxItems: 9
73
74  phys:
75    maxItems: 1
76
77  phy-names:
78    deprecated: true
79    const: dsi
80
81  syscon-sfpb:
82    description: A phandle to mmss_sfpb syscon node (only for DSIv2).
83    $ref: /schemas/types.yaml#/definitions/phandle
84
85  qcom,dual-dsi-mode:
86    type: boolean
87    description: |
88      Indicates if the DSI controller is driving a panel which needs
89      2 DSI links.
90
91  qcom,master-dsi:
92    type: boolean
93    description: |
94      Indicates if the DSI controller is the master DSI controller when
95      qcom,dual-dsi-mode enabled.
96
97  qcom,sync-dual-dsi:
98    type: boolean
99    description: |
100      Indicates if the DSI controller needs to sync the other DSI controller
101      with MIPI DCS commands when qcom,dual-dsi-mode enabled.
102
103  assigned-clocks:
104    minItems: 2
105    maxItems: 4
106    description: |
107      Parents of "byte" and "pixel" for the given platform.
108      For DSIv2 platforms this should contain "byte", "esc", "src" and
109      "pixel_src" clocks.
110
111  assigned-clock-parents:
112    minItems: 2
113    maxItems: 4
114    description: |
115      The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block.
116
117  power-domains:
118    maxItems: 1
119
120  operating-points-v2: true
121
122  opp-table:
123    type: object
124
125  ports:
126    $ref: /schemas/graph.yaml#/properties/ports
127    description: |
128      Contains DSI controller input and output ports as children, each
129      containing one endpoint subnode.
130
131    properties:
132      port@0:
133        $ref: /schemas/graph.yaml#/$defs/port-base
134        unevaluatedProperties: false
135        description: |
136          Input endpoints of the controller.
137        properties:
138          endpoint:
139            $ref: /schemas/media/video-interfaces.yaml#
140            unevaluatedProperties: false
141            properties:
142              data-lanes:
143                maxItems: 4
144                minItems: 1
145                items:
146                  enum: [ 0, 1, 2, 3 ]
147
148      port@1:
149        $ref: /schemas/graph.yaml#/$defs/port-base
150        unevaluatedProperties: false
151        description: |
152          Output endpoints of the controller.
153        properties:
154          endpoint:
155            $ref: /schemas/media/video-interfaces.yaml#
156            unevaluatedProperties: false
157            properties:
158              data-lanes:
159                maxItems: 4
160                minItems: 1
161                items:
162                  enum: [ 0, 1, 2, 3 ]
163
164    required:
165      - port@0
166      - port@1
167
168  avdd-supply:
169    description:
170      Phandle to vdd regulator device node
171
172  refgen-supply:
173    description:
174      Phandle to REFGEN regulator device node
175
176  vcca-supply:
177    description:
178      Phandle to vdd regulator device node
179
180  vdd-supply:
181    description:
182      VDD regulator
183
184  vddio-supply:
185    description:
186      VDD-IO regulator
187
188  vdda-supply:
189    description:
190      VDDA regulator
191
192required:
193  - compatible
194  - reg
195  - reg-names
196  - interrupts
197  - clocks
198  - clock-names
199  - phys
200  - assigned-clocks
201  - assigned-clock-parents
202  - ports
203
204allOf:
205  - $ref: ../dsi-controller.yaml#
206  - if:
207      properties:
208        compatible:
209          contains:
210            enum:
211              - qcom,apq8064-dsi-ctrl
212    then:
213      properties:
214        clocks:
215          maxItems: 7
216        clock-names:
217          items:
218            - const: iface
219            - const: bus
220            - const: core_mmss
221            - const: src
222            - const: byte
223            - const: pixel
224            - const: core
225
226  - if:
227      properties:
228        compatible:
229          contains:
230            enum:
231              - qcom,msm8916-dsi-ctrl
232    then:
233      properties:
234        clocks:
235          maxItems: 6
236        clock-names:
237          items:
238            - const: mdp_core
239            - const: iface
240            - const: bus
241            - const: byte
242            - const: pixel
243            - const: core
244
245  - if:
246      properties:
247        compatible:
248          contains:
249            enum:
250              - qcom,msm8953-dsi-ctrl
251    then:
252      properties:
253        clocks:
254          maxItems: 6
255        clock-names:
256          items:
257            - const: mdp_core
258            - const: iface
259            - const: bus
260            - const: byte
261            - const: pixel
262            - const: core
263
264  - if:
265      properties:
266        compatible:
267          contains:
268            enum:
269              - qcom,msm8226-dsi-ctrl
270              - qcom,msm8974-dsi-ctrl
271    then:
272      properties:
273        clocks:
274          maxItems: 7
275        clock-names:
276          items:
277            - const: mdp_core
278            - const: iface
279            - const: bus
280            - const: byte
281            - const: pixel
282            - const: core
283            - const: core_mmss
284
285  - if:
286      properties:
287        compatible:
288          contains:
289            enum:
290              - qcom,msm8996-dsi-ctrl
291    then:
292      properties:
293        clocks:
294          maxItems: 7
295        clock-names:
296          items:
297            - const: mdp_core
298            - const: byte
299            - const: iface
300            - const: bus
301            - const: core_mmss
302            - const: pixel
303            - const: core
304
305  - if:
306      properties:
307        compatible:
308          contains:
309            enum:
310              - qcom,msm8998-dsi-ctrl
311              - qcom,sm6125-dsi-ctrl
312              - qcom,sm6350-dsi-ctrl
313    then:
314      properties:
315        clocks:
316          maxItems: 6
317        clock-names:
318          items:
319            - const: byte
320            - const: byte_intf
321            - const: pixel
322            - const: core
323            - const: iface
324            - const: bus
325
326  - if:
327      properties:
328        compatible:
329          contains:
330            enum:
331              - qcom,sc7180-dsi-ctrl
332              - qcom,sc7280-dsi-ctrl
333              - qcom,sm8150-dsi-ctrl
334              - qcom,sm8250-dsi-ctrl
335              - qcom,sm8350-dsi-ctrl
336              - qcom,sm8450-dsi-ctrl
337              - qcom,sm8550-dsi-ctrl
338              - qcom,sm8650-dsi-ctrl
339    then:
340      properties:
341        clocks:
342          maxItems: 6
343        clock-names:
344          items:
345            - const: byte
346            - const: byte_intf
347            - const: pixel
348            - const: core
349            - const: iface
350            - const: bus
351
352  - if:
353      properties:
354        compatible:
355          contains:
356            enum:
357              - qcom,sdm660-dsi-ctrl
358    then:
359      properties:
360        clocks:
361          maxItems: 9
362        clock-names:
363          items:
364            - const: mdp_core
365            - const: byte
366            - const: byte_intf
367            - const: mnoc
368            - const: iface
369            - const: bus
370            - const: core_mmss
371            - const: pixel
372            - const: core
373
374  - if:
375      properties:
376        compatible:
377          contains:
378            enum:
379              - qcom,sdm845-dsi-ctrl
380              - qcom,sm6115-dsi-ctrl
381              - qcom,sm6375-dsi-ctrl
382    then:
383      properties:
384        clocks:
385          maxItems: 6
386        clock-names:
387          items:
388            - const: byte
389            - const: byte_intf
390            - const: pixel
391            - const: core
392            - const: iface
393            - const: bus
394
395unevaluatedProperties: false
396
397examples:
398  - |
399     #include <dt-bindings/interrupt-controller/arm-gic.h>
400     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
401     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
402     #include <dt-bindings/power/qcom-rpmpd.h>
403
404     dsi@ae94000 {
405           compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
406           reg = <0x0ae94000 0x400>;
407           reg-names = "dsi_ctrl";
408
409           #address-cells = <1>;
410           #size-cells = <0>;
411
412           interrupt-parent = <&mdss>;
413           interrupts = <4>;
414
415           clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
416                    <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
417                    <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
418                    <&dispcc DISP_CC_MDSS_ESC0_CLK>,
419                    <&dispcc DISP_CC_MDSS_AHB_CLK>,
420                    <&dispcc DISP_CC_MDSS_AXI_CLK>;
421           clock-names = "byte",
422                         "byte_intf",
423                         "pixel",
424                         "core",
425                         "iface",
426                         "bus";
427
428           phys = <&dsi0_phy>;
429           phy-names = "dsi";
430
431           assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
432           assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
433
434           power-domains = <&rpmhpd SC7180_CX>;
435           operating-points-v2 = <&dsi_opp_table>;
436
437           ports {
438                  #address-cells = <1>;
439                  #size-cells = <0>;
440
441                  port@0 {
442                          reg = <0>;
443                          dsi0_in: endpoint {
444                                   remote-endpoint = <&dpu_intf1_out>;
445                          };
446                  };
447
448                  port@1 {
449                          reg = <1>;
450                          dsi0_out: endpoint {
451                                   remote-endpoint = <&sn65dsi86_in>;
452                                   data-lanes = <0 1 2 3>;
453                          };
454                  };
455           };
456     };
457...
458