| /freebsd/sys/contrib/device-tree/Bindings/media/i2c/ |
| H A D | aptina,mt9p031.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
15 simple two-wire serial interface.
20 - aptina,mt9p006
21 - aptina,mt9p031
22 - aptina,mt9p031m
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| H A D | mt9p031.txt | 1 * Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
3 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor with
5 two-wire serial interface.
8 - compatible: value should be either one among the following
12 - input-clock-frequency: Input clock frequency.
14 - pixel-clock-frequency: Pixel clock frequency.
17 - reset-gpios: Chip reset GPIO
20 Documentation/devicetree/bindings/media/video-interfaces.txt.
30 reset-gpios = <&gpio3 30 0>;
34 input-clock-frequency = <6000000>;
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| H A D | imx258.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
12 description: |-
13 IMX258 is a diagonal 5.867mm (Type 1/3.06) 13 Mega-pixel CMOS active pixel
14 type stacked image sensor with a square pixel array of size 4208 x 3120. It
16 CSI-2.
22 assigned-clocks: true
23 assigned-clock-parents: true
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| H A D | sony,imx258.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
12 description: |-
13 IMX258 is a diagonal 5.867mm (Type 1/3.06) 13 Mega-pixel CMOS active pixel
14 type stacked image sensor with a square pixel array of size 4208 x 3120. It
16 CSI-2. The sensor exists in two different models, a standard variant
17 (IMX258) and a variant with phase detection autofocus (IMX258-PDAF).
24 - sony,imx258
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| H A D | ov7251.txt | 1 * Omnivision 1/7.5-Inch B&W VGA CMOS Digital Image Sensor
3 The Omnivision OV7251 is a 1/7.5-Inch CMOS active pixel digital image sensor
8 - compatible: Value should be "ovti,ov7251".
9 - clocks: Reference to the xclk clock.
10 - clock-names: Should be "xclk".
11 - clock-frequency: Frequency of the xclk clock.
12 - enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
14 - vdddo-supply: Chip digital IO regulator.
15 - vdda-supply: Chip analog regulator.
16 - vddd-supply: Chip digital core regulator.
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| H A D | ov5645.txt | 1 * Omnivision 1/4-Inch 5Mp CMOS Digital Image Sensor
3 The Omnivision OV5645 is a 1/4-Inch CMOS active pixel digital image sensor with
8 - compatible: Value should be "ovti,ov5645".
9 - clocks: Reference to the xclk clock.
10 - clock-names: Should be "xclk".
11 - clock-frequency: Frequency of the xclk clock.
12 - enable-gpios: Chip enable GPIO. Polarity is GPIO_ACTIVE_HIGH. This corresponds
14 - reset-gpios: Chip reset GPIO. Polarity is GPIO_ACTIVE_LOW. This corresponds to
16 - vdddo-supply: Chip digital IO regulator.
17 - vdda-supply: Chip analog regulator.
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| H A D | imx290.txt | 1 * Sony IMX290 1/2.8-Inch CMOS Image Sensor
3 The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with
4 Square Pixel for Color Cameras. It is programmable through I2C and 4-wire
6 Low voltage LVDS DDR output and CSI-2 serial data output. The CSI-2 bus is the
10 - compatible: Should be "sony,imx290"
11 - reg: I2C bus address of the device
12 - clocks: Reference to the xclk clock.
13 - clock-names: Should be "xclk".
14 - clock-frequency: Frequency of the xclk clock in Hz.
15 - vdddo-supply: Sensor digital IO regulator.
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| H A D | sony,imx214.txt | 1 * Sony 1/3.06-Inch 13.13Mp CMOS Digital Image Sensor
3 The Sony imx214 is a 1/3.06-inch CMOS active pixel digital image sensor with
6 Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a maximum
11 - compatible: Shall be "sony,imx214".
12 - reg: I2C bus address of the device. Depending on how the sensor is wired,
14 - enable-gpios: GPIO descriptor for the enable pin.
15 - vdddo-supply: Chip digital IO regulator (1.8V).
16 - vdda-supply: Chip analog regulator (2.7V).
17 - vddd-supply: Chip digital core regulator (1.12V).
18 - clocks: Reference to the xclk clock.
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| H A D | sony,imx214.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony 1/3.06-Inch 13.13MP CMOS Digital Image Sensor
10 - Ricardo Ribalda <ribalda@kernel.org>
13 The Sony IMX214 is a 1/3.06-inch CMOS active pixel digital image sensor with
15 interface. Image data is sent through MIPI CSI-2, through 2 or 4 lanes at a
19 - $ref: /schemas/media/video-interface-devices.yaml#
27 - 0x10
28 - 0x1a
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| H A D | sony,imx290.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony IMX290 1/2.8-Inch CMOS Image Sensor
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with Square
15 Pixel, available in either mono or colour variants. It is programmable
16 through I2C and 4-wire interfaces.
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | fsl,plldig.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,plldig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
13 NXP LS1028A has a clock domain PXLCLK0 used for the Display output
15 which generate and offers pixel clocks to Display.
19 const: fsl,ls1028a-plldig
27 '#clock-cells':
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | cirrus,clps711x-fb.txt | 4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
11 - bits-pe
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| H A D | ssd1307fb.txt | 4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
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| H A D | mxsfb.txt | 6 - compatible: Should be "fsl,imx23-lcdif" for i.MX23.
7 Should be "fsl,imx28-lcdif" for i.MX28.
8 Should be "fsl,imx6sx-lcdif" for i.MX6SX.
9 Should be "fsl,imx8mq-lcdif" for i.MX8MQ.
10 - reg: Address and length of the register set for LCDIF
11 - interrupts: Should contain LCDIF interrupt
12 - clocks: A list of phandle + clock-specifier pairs, one for each
13 entry in 'clock-names'.
14 - clock-names: A list of clock names. For MXSFB it should contain:
15 - "pix" for the LCDIF block clock
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| H A D | wm,wm8505-fb.txt | 2 -----------------------------------------------------
5 - compatible : "wm,wm8505-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - bits-per-pixel : bit depth of framebuffer (16 or 32)
10 - display-timings: see display-timing.txt for information
15 compatible = "wm,wm8505-fb";
17 bits-per-pixel = <16>;
19 display-timings {
20 native-mode = <&timing0>;
22 clock-frequency = <0>; /* unused but required */
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| H A D | via,vt8500-fb.txt | 2 -----------------------------------------------------
5 - compatible : "via,vt8500-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - interrupts : framebuffer controller interrupt
8 - bits-per-pixel : bit depth of framebuffer (16 or 32)
11 - display-timings: see display-timing.txt for information
16 compatible = "via,vt8500-fb";
19 bits-per-pixel = <16>;
21 display-timings {
22 native-mode = <&timing0>;
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| H A D | atmel,lcdc-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
17 interface and a look-up table to allow palletized display configurations. The
19 resolutions, window sizes, image formats and pixel depths.
26 - required: [ 'atmel,dmacon' ]
27 - required: [ 'atmel,lcdcon2' ]
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| /freebsd/sys/contrib/device-tree/Bindings/display/panel/ |
| H A D | panel-mipi-dbi-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Noralf Trønnes <noralf@tronnes.org>
23 - Power:
24 - Vdd: Power supply for display module
25 Called power-supply in this binding.
26 - Vddi: Logic level supply for interface signals
27 Called io-supply in this binding.
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| H A D | panel-timing.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | samsung,mipi-dsim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | logicpd-torpedo-37xx-devkit.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 /dts-v1/;
6 #include "logicpd-torpedo-som.dtsi"
7 #include "omap-gpmc-smsc9221.dtsi"
8 #include "logicpd-torped
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| /freebsd/sys/contrib/device-tree/src/arm/broadcom/ |
| H A D | bcm283x.dtsi | 1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
21 #address-cells = <1>;
22 #size-cells = <1>;
30 stdout-path = "serial0:115200n8";
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| /freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | fsl,imx-fb.txt | 6 - compatible : "fsl,<chip>-fb", chip should be imx1 or imx21
7 - reg : Should contain 1 register ranges(address and length)
8 - interrupts : One interrupt of the fb dev
11 - display: Phandle to a display node as described in
12 Documentation/devicetree/bindings/display/panel/display-timing.txt
14 - bits-per-pixel: Bits per pixel
15 - fsl,pcr: LCDC PCR value
17 - fsl,aus-mode: boolean to enable AUS mode (only for imx21)
20 - lcd-supply: Regulator for LCD supply voltage.
21 - fsl,dmacr: DMA Control Register value. This is optional. By default, the
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| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | nxp,imx-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
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| H A D | nxp,imx7-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
10 - Rui Miguel Silva <rmfrfs@gmail.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 description: |-
14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
19 While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
[all …]
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