| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 992 display_e2e_pipe_params_st *pipes) in dcn20_populate_dml_writeback_from_context() argument
1005 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0; in dcn20_populate_dml_writeback_from_context()
1006 pipes[pipe_cnt].dout.num_active_wb++; in dcn20_populate_dml_writeback_from_context()
1007 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height; in dcn20_populate_dml_writeback_from_context()
1008 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width; in dcn20_populate_dml_writeback_from_context()
1009 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width; in dcn20_populate_dml_writeback_from_context()
1010 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height; in dcn20_populate_dml_writeback_from_context()
1011 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1012 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1; in dcn20_populate_dml_writeback_from_context()
1013 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c; in dcn20_populate_dml_writeback_from_context()
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| H A D | dcn20_fpu.h | 33 display_e2e_pipe_params_st *pipes);
37 display_e2e_pipe_params_st *pipes,
41 display_e2e_pipe_params_st *pipes,
46 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
65 bool fast_validate, display_e2e_pipe_params_st *pipes);
77 display_e2e_pipe_params_st *pipes,
80 fast_validate, display_e2e_pipe_params_st *pipes);
87 display_e2e_pipe_params_st *pipes);
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 258 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) in dcn30_fpu_populate_dml_writeback_from_context() argument
275 pipes[pipe_cnt].dout.wb_enable = 0; in dcn30_fpu_populate_dml_writeback_from_context()
276 pipes[pipe_cnt].dout.num_active_wb = 0; in dcn30_fpu_populate_dml_writeback_from_context()
282 pipes[pipe_cnt].dout.wb_enable = 1; in dcn30_fpu_populate_dml_writeback_from_context()
283 pipes[pipe_cnt].dout.num_active_wb++; in dcn30_fpu_populate_dml_writeback_from_context()
326 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz, in dcn30_fpu_populate_dml_writeback_from_context()
333 pipes[pipe_cnt].pipe.dest.htotal, in dcn30_fpu_populate_dml_writeback_from_context()
338 pipes[pipe_cnt].dout.wb = dout_wb; in dcn30_fpu_populate_dml_writeback_from_context()
349 display_e2e_pipe_params_st *pipes, in dcn30_fpu_set_mcif_arb_params() argument
358 wb_arb_params->cli_watermark[i] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000; in dcn30_fpu_set_mcif_arb_params()
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| H A D | dcn30_fpu.h | 36 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
40 display_e2e_pipe_params_st *pipes,
48 display_e2e_pipe_params_st *pipes,
68 display_e2e_pipe_params_st *pipes,
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| H A D | dcn301_fpu.c | 296 display_e2e_pipe_params_st *pipes, in calculate_wm_set_for_vlevel() argument
303 pipes[0].clks_cfg.voltage = vlevel; in calculate_wm_set_for_vlevel()
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
305 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
311 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
312 …wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) … in calculate_wm_set_for_vlevel()
313 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
314 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
315 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
316 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| H A D | dcn314_fpu.c | 308 display_e2e_pipe_params_st *pipes, in dcn314_populate_dml_pipes_from_context_fpu() argument
319 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate); in dcn314_populate_dml_pipes_from_context_fpu()
334 pipes[pipe_cnt].pipe.dest.vtotal = pipe->stream->adjust.v_total_min; in dcn314_populate_dml_pipes_from_context_fpu()
336 pipes[pipe_cnt].pipe.dest.vtotal = timing->v_total; in dcn314_populate_dml_pipes_from_context_fpu()
340 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn314_populate_dml_pipes_from_context_fpu()
341 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn314_populate_dml_pipes_from_context_fpu()
346 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn314_populate_dml_pipes_from_context_fpu()
347 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn314_populate_dml_pipes_from_context_fpu()
348 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn314_populate_dml_pipes_from_context_fpu()
357 … pipes[i].pipe.src.hostvm = dc->vm_pa_config.is_hvm_enabled || dc->res_pool->hubbub->riommu_active; in dcn314_populate_dml_pipes_from_context_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | dcn32_fpu.c | 277 display_e2e_pipe_params_st *pipes, in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() argument
293 dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false); in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
295 /* for subvp + DRR case, if subvp pipes are still present we support pstate */ in dcn32_find_dummy_latency_index_for_fw_based_mclk_switch()
322 * dcn32_helper_populate_phantom_dlg_params - Get DLG params for phantom pipes
326 * @pipes: [in] DML pipe params array
329 * This function must be called AFTER the phantom pipes are added to context
330 * and run through DML (so that the DLG params for the phantom pipes can be
331 * populated), and BEFORE we program the timing for the phantom pipes.
335 display_e2e_pipe_params_st *pipes, in dcn32_helper_populate_phantom_dlg_params() argument
349 pipes[pipe_idx].pipe.dest.vstartup_start = in dcn32_helper_populate_phantom_dlg_params()
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| H A D | dcn32_fpu.h | 36 display_e2e_pipe_params_st *pipes,
43 display_e2e_pipe_params_st *pipes,
49 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes,
63 display_e2e_pipe_params_st *pipes,
69 void dcn32_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes,
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| /linux/drivers/platform/goldfish/ |
| H A D | goldfish_pipe.c | 126 /* pipe ID - index into goldfish_pipe_dev::pipes array */
143 /* doubly linked list of signalled pipes, protected by
176 * - pipes, pipes_capacity
177 * - [*pipes, *pipes + pipes_capacity) - array data
182 * in all allocated pipes
186 * the only operation that happens often is the signalled pipes array
194 * Array of the pipes of |pipes_capacity| elements,
197 struct goldfish_pipe **pipes; member
203 /* Head of a doubly linked list of signalled pipes */
521 pipe = dev->pipes[id]; in signalled_pipes_add_locked()
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| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | mpo-overview.rst | 50 For this hardware example, we have 4 pipes (if you don't know what AMD pipe
53 configuration for optimal single display output (e.g., 2 pipes per plane).
56 display - will see 4 pipes in use, 2 per plane.
204 the two displays, we need to use 2 pipes. See the example below where we avoid
207 - 1 display (1 pipe) + MPO (1 pipe), we will use two pipes
208 - 2 displays (2 pipes) + MPO (1-2 pipes); we will use 4 pipes. MPO in the
209 middle of both displays needs 2 pipes.
210 - 3 Displays (3 pipes) + MPO (1-2 pipes), we need 5 pipes.
217 * When ASIC has 3 pipes, AMD hardware can NOT support 2 displays with MPO
218 * When ASIC has 4 pipes, AMD hardware can NOT support 3 displays with MPO
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 46 const display_e2e_pipe_params_st *pipes,
54 const display_e2e_pipe_params_st *pipes, in dml_get_voltage_level() argument
60 || memcmp(pipes, mode_lib->vba.cache_pipes, in dml_get_voltage_level()
65 memcpy(mode_lib->vba.cache_pipes, pipes, sizeof(*pipes) * num_pipes); in dml_get_voltage_level()
68 if (need_recalculate && pipes[0].clks_cfg.dppclk_mhz != 0) in dml_get_voltage_level()
82 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
84 recalculate_params(mode_lib, pipes, num_pipes); \
130 …attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_…
133 recalculate_params(mode_lib, pipes, num_pipes); \
209 const display_e2e_pipe_params_st *pipes, in get_total_immediate_flip_bytes() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn35/ |
| H A D | dcn35_fpu.c | 437 display_e2e_pipe_params_st *pipes, in dcn35_populate_dml_pipes_from_context_fpu() argument
446 dcn31_populate_dml_pipes_from_context(dc, context, pipes, in dcn35_populate_dml_pipes_from_context_fpu()
466 pipes[pipe_cnt].pipe.dest.vtotal = in dcn35_populate_dml_pipes_from_context_fpu()
468 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - in dcn35_populate_dml_pipes_from_context_fpu()
469 pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
472 pipes[pipe_cnt].pipe.dest.vblank_nom = timing->v_total - pipes[pipe_cnt].pipe.dest.vactive; in dcn35_populate_dml_pipes_from_context_fpu()
473 pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, num_lines); in dcn35_populate_dml_pipes_from_context_fpu()
478 pipes[pipe_cnt].pipe.dest.vblank_nom = in dcn35_populate_dml_pipes_from_context_fpu()
479 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn35_populate_dml_pipes_from_context_fpu()
480 …pipes[pipe_cnt].pipe.dest.vblank_nom = min(pipes[pipe_cnt].pipe.dest.vblank_nom, max_allowed_vblan… in dcn35_populate_dml_pipes_from_context_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 445 void dcn31_zero_pipe_dcc_fraction(display_e2e_pipe_params_st *pipes, in dcn31_zero_pipe_dcc_fraction() argument
450 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; in dcn31_zero_pipe_dcc_fraction()
451 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; in dcn31_zero_pipe_dcc_fraction()
484 display_e2e_pipe_params_st *pipes, in dcn31_calculate_wm_and_dlg_fp() argument
506 pipes[0].clks_cfg.voltage = vlevel; in dcn31_calculate_wm_and_dlg_fp()
507 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
508 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
511 get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000; in dcn31_calculate_wm_and_dlg_fp()
513 …if (get_stutter_period(&context->bw_ctx.dml, pipes, pipe_cnt) < dc->debug.minimum_z8_residency_tim… in dcn31_calculate_wm_and_dlg_fp()
523 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
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| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 17 -- Seekable pipes
23 -- Channels, pipes, and the message channel
85 project to another (the number of data pipes needed in each direction and
90 Xillybus presents independent data streams, which resemble pipes or TCP/IP
125 possibly pressing CTRL-C as some stage, even though the xillybus_* pipes have
128 The driver and hardware are designed to behave sensibly as pipes, including:
138 device files are treated like two independent pipes (except for sharing a
144 Xillybus pipes are configured (on the IP core) to be either synchronous or
154 For FPGA to host pipes, asynchronous pipes allow data transfer from the FPGA
156 has been requested by a read() call. On synchronous pipes, only the amount
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource_helpers.c | 112 /* merge pipes if necessary */ in dcn32_merge_pipes_for_subvp()
116 // For now merge all pipes for SubVP since pipe split case isn't supported yet in dcn32_merge_pipes_for_subvp()
118 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ in dcn32_merge_pipes_for_subvp()
295 * number of DET for that given plane will be split among the pipes driving that plane.
302 * among those pipes.
303 * 4. Assign the DET override to the DML pipes.
307 * @pipes: Array of DML pipes
313 display_e2e_pipe_params_st *pipes) in dcn32_determine_det_override() argument
342 /* Note: pipe_plane_count indicates the number of pipes to be used for a in dcn32_determine_det_override()
372 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE; in dcn32_determine_det_override()
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| H A D | dcn32_resource.c | 1684 display_e2e_pipe_params_st *pipes, in dcn32_enable_phantom_stream() argument
1700 …dcn32_set_phantom_stream_timing(dc, context, ref_pipe, phantom_stream, pipes, pipe_cnt, dc_pipe_id… in dcn32_enable_phantom_stream()
1711 display_e2e_pipe_params_st *pipes, in dcn32_add_phantom_pipes() argument
1721 phantom_stream = dcn32_enable_phantom_stream(dc, context, pipes, pipe_cnt, index); in dcn32_add_phantom_pipes()
1730 // Build scaling params for phantom pipes which were newly added. in dcn32_add_phantom_pipes()
1731 // We determine which phantom pipes were added by comparing with in dcn32_add_phantom_pipes()
1738 // Log / remove phantom pipes since failed to build scaling params in dcn32_add_phantom_pipes()
1752 …display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_par… in dml1_validate() local
1764 if (!pipes) in dml1_validate()
1768 out = dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate); in dml1_validate()
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| /linux/drivers/gpu/drm/arm/display/komeda/ |
| H A D | komeda_event.c | 110 return (a->pipes[0] | a->pipes[1]) & in is_new_frame()
120 u64 evts_mask = evts->global | evts->pipes[0] | evts->pipes[1]; in komeda_print_events()
146 komeda_sprintf(&str, ", pipes[0]: "); in komeda_print_events()
147 evt_str(&str, evts->pipes[0]); in komeda_print_events()
148 komeda_sprintf(&str, ", pipes[1]: "); in komeda_print_events()
149 evt_str(&str, evts->pipes[1]); in komeda_print_events()
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| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_smp.h | 25 * In some hw, some blocks are statically allocated for certain pipes
40 * for the newly assigned pipes, so we don't take away blocks
41 * assigned to pipes that are still scanning out
43 * released clients, since at that point old pipes are no longer
53 /* assigned pipes (hw updated at _prepare_commit()): */
56 /* released pipes (hw updated at _complete_commit()): */
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.h | 51 display_e2e_pipe_params_st *pipes,
64 display_e2e_pipe_params_st *pipes,
71 display_e2e_pipe_params_st *pipes,
76 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
80 display_e2e_pipe_params_st *pipes,
106 display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel);
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_mall_phantom.c | 52 // Find the phantom pipes in dml2_helper_calculate_num_ways_for_subvp()
105 /* merge pipes if necessary */ in merge_pipes_for_subvp()
109 // For now merge all pipes for SubVP since pipe split case isn't supported yet in merge_pipes_for_subvp()
111 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */ in merge_pipes_for_subvp()
174 * dcn32_get_num_free_pipes: Calculate number of free pipes
183 * Number of free pipes available in the context
209 * We enter this function if we are Sub-VP capable (i.e. enough pipes available)
213 * The number of pipes used for the chosen surface must be less than or equal to the
214 * number of free pipes available.
223 * @param index: [out] dc pipe index for the pipe chosen to have phantom pipes assigned
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | resource.h | 205 * |PIPE IDX| DPP PIPES | OPP HEADS | OTG MASTER |
226 * OTG Master pipe ---1--------1..N--- OPP Head pipes
228 * OPP Head pipe ---1--------0..N--- DPP pipes
232 * Plane ---1--------1..N--- DPP pipes
242 /* OTG master pipe - the master pipe of its OPP head pipes with a
243 * functional OTG. It merges all its OPP head pipes pixel data in ODM
248 * can output pixel data from its OPP head pipes' test pattern
318 * Update ODM slice count by acquiring or releasing pipes. If new slices need
323 * return - true if ODM slices are updated and required pipes are acquired. All
340 * Update MPC slice count by acquiring or releasing DPP pipes. If new slices
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| /linux/drivers/net/wireless/ath/ath6kl/ |
| H A D | usb.c | 29 /* tx/rx pipes for usb */
70 struct ath6kl_usb_pipe pipes[ATH6KL_USB_PIPE_MAX]; member
255 ath6kl_usb_free_pipe_resources(&ar_usb->pipes[i]); in ath6kl_usb_cleanup_pipe_resources()
313 ath6kl_dbg(ATH6KL_DBG_USB, "setting up USB Pipes using interface\n"); in ath6kl_usb_setup_pipe_resources()
315 /* walk descriptors and setup pipes */ in ath6kl_usb_setup_pipe_resources()
358 pipe = &ar_usb->pipes[pipe_num]; in ath6kl_usb_setup_pipe_resources()
474 if (ar_usb->pipes[i].ar_usb != NULL) in ath6kl_usb_flush_all()
475 usb_kill_anchored_urbs(&ar_usb->pipes[i].urb_submitted); in ath6kl_usb_flush_all()
489 * ar_usb->pipes[ATH6KL_USB_PIPE_RX_CTRL].urb_cnt_thresh = in ath6kl_usb_start_recv_pipes()
490 * ar_usb->pipes[ATH6KL_USB_PIPE_RX_CTRL].urb_alloc/2; in ath6kl_usb_start_recv_pipes()
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| /linux/drivers/gpu/drm/tidss/ |
| H A D | tidss_kms.c | 120 struct pipe pipes[TIDSS_MAX_PORTS]; in tidss_dispc_modeset_init() local
177 pipes[num_pipes].hw_videoport = i; in tidss_dispc_modeset_init()
178 pipes[num_pipes].bridge = bridge; in tidss_dispc_modeset_init()
179 pipes[num_pipes].enc_type = enc_type; in tidss_dispc_modeset_init()
204 tcrtc = tidss_crtc_create(tidss, pipes[i].hw_videoport, in tidss_dispc_modeset_init()
213 ret = tidss_encoder_create(tidss, pipes[i].bridge, in tidss_dispc_modeset_init()
214 pipes[i].enc_type, in tidss_dispc_modeset_init()
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| /linux/drivers/staging/media/atomisp/pci/ |
| H A D | ia_css_stream_public.h | 117 to system memory and run pipes in offline mode */
157 * create the internal structures and fill in the configuration data and pipes
162 * @param[in] num_pipes The number of pipes to incorporate in the stream.
163 * @param[in] pipes The pipes.
167 * This function will create a stream with a given configuration and given pipes.
172 struct ia_css_pipe *pipes[],
213 * NOTE: this function will send stop event to pipes belong to this
232 * Destroy the stream and all the pipes related to it.
462 * update all pipes in the stream.
466 * stream. For image pipes that do not execute any ISP filters, this
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn31/ |
| H A D | dcn31_resource.h | 45 display_e2e_pipe_params_st *pipes,
50 display_e2e_pipe_params_st *pipes,
55 display_e2e_pipe_params_st *pipes);
59 display_e2e_pipe_params_st *pipes,
|