Home
last modified time | relevance | path

Searched +full:pins +full:- +full:spi +full:- +full:mi (Results 1 – 10 of 10) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-mt65xx.txt1 Binding for MTK SPI controller
4 - compatible: should be one of the following.
5 - mediatek,mt2701-spi: for mt2701 platforms
6 - mediatek,mt2712-spi: for mt2712 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms
8 - mediatek,mt6765-spi: for mt6765 platforms
9 - mediatek,mt7622-spi: for mt7622 platforms
10 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
11 - mediatek,mt8135-spi: for mt8135 platforms
12 - mediatek,mt8173-spi: for mt8173 platforms
[all …]
H A Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Bus controller for MediaTek ARM SoCs
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmediatek,mt8195-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8195 Pin controller is used to control SoC pins.
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
[all …]
H A Dpinctrl-mt8195.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8195.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The Mediatek's Pin controller is used to control SoC pins.
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
[all …]
H A Dmediatek,mt8188-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
13 The MediaTek's MT8188 Pin controller is used to control SoC pins.
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
[all …]
H A Dmediatek,mt8186-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8186 Pin controller is used to control SoC pins.
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
[all …]
H A Dpinctrl-mt8186.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8186.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The Mediatek's Pin controller is used to control SoC pins.
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
21 stdout-path = "serial0:115200n8";
25 compatible = "pwm-backlight";
27 power-supply = <&reg_vsys>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
31 default-brightness-level = <576>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-binding
[all...]
/freebsd/sys/dev/bxe/
H A Dbxe_elink.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
501 /* These pins configure the BCM84823 interface to MAC after reset. */
504 /* These pins configure the BCM84823 interface to Line after reset. */
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
936 (_phy)->def_md_devad, \
942 (_phy)->def_md_devad, \
[all …]