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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4-var-som-om44.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012 Variscite Ltd. - https://www.variscite.com
7 #include "omap4-mcpdm.dtsi"
10 model = "Variscite VAR-SOM-OM44";
11 compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
19 compatible = "ti,abe-twl6040";
20 ti,model = "VAR-SOM-OM44";
22 ti,mclk-freq = <38400000>;
27 ti,audio-routing =
36 compatible = "usb-nop-xceiv";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ul-tqma6ul2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulx-common.dtsi"
12 model = "TQ-Systems TQMa6UL2 SoM";
13 compatible = "tq,imx6ul-tqma6ul2", "fsl,imx6ul";
17 fsl,tuning-step = <6>;
22 fsl,pins = <
33 /* rst */
[all …]
H A Dimx6ul-tqma6ul2l.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulxl-common.dtsi"
12 model = "TQ-Systems TQMa6UL2L SoM";
13 compatible = "tq,imx6ul-tqma6ul2l", "fsl,imx6ul";
17 fsl,tuning-step = <6>;
22 fsl,pins = <
33 /* rst */
[all …]
H A Dimx6ull-tqma6ull2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulx-common.dtsi"
12 model = "TQ-Systems TQMa6ULL2 SoM";
13 compatible = "tq,imx6ull-tqma6ull2", "fsl,imx6ull";
17 fsl,tuning-step = <6>;
19 max-frequency = <99000000>;
20 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
[all …]
H A Dimx6ull-tqma6ull2l.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 #include "imx6ul-tqma6ul-common.dtsi"
9 #include "imx6ul-tqma6ulxl-common.dtsi"
13 compatible = "tq,imx6ull-tqma6ull2l", "fsl,imx6ull";
17 fsl,tuning-step = <6>;
19 max-frequency = <99000000>;
20 assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
21 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6795-sony-xperia-m5.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "sony,xperia-m5", "mediatek,mt6795";
15 chassis-type = "handset";
26 compatible = "led-backlight";
29 default-brightnes
[all...]
H A Dmt7986a-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
[all …]
H A Dmt8365-evk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
26 stdout-path = "serial0:921600n8";
31 compatible = "linaro,optee-tz";
36 gpio-keys {
[all …]
H A Dmt8195-demo.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14 #include <dt-bindings/regulator/mediatek,mt6360-regulato
[all...]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmediatek,mt7621-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7621-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
16 pins is not supported. There is no pinconf support.
20 const: ralink,mt7621-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
[all …]
H A Dralink,mt7621-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,mt7621-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
16 pins is not supported. There is no pinconf support.
20 const: ralink,mt7621-pinctrl
23 '-pins$':
26 '^(.*-)?pinmux$':
[all …]
H A Dmediatek,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
16 pins is not supported. There is no pinconf support.
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
[all …]
H A Dralink,rt2880-pinmux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,rt2880-pinmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
13 The rt2880 pinmux can only set the muxing of pin groups. Muxing indiviual pins
18 const: ralink,rt2880-pinmux
21 '-pins$':
24 '^(.*-)?pinmux$':
27 $ref: pinmux-node.yaml#
[all …]
H A Dlantiq,pinctrl-falcon.txt4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
14 pin, a group, or a list of pins or groups. This configuration can include the
16 pull-up and open-drain
31 Required subnode-properties:
32 - lantiq,groups : An array of strings. Each string contains the name of a group.
34 - lantiq,function: A string containing the name of the function to mux to the
44 rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm
49 Required subnode-properties:
[all …]
H A Dralink,mt7620-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/ralink,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
16 pins is not supported. There is no pinconf support.
20 const: ralink,mt7620-pinctrl
23 '-pins$':
26 '^(.*-)?pinmux$':
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-kontron-n801x-s.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 /dts-v1/;
8 #include "imx8mm-kontron-n801x-som.dtsi"
12 compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
19 osc_can: clock-osc-can {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <16000000>;
23 clock-output-names = "osc-can";
27 compatible = "gpio-leds";
[all …]
H A Dimx8mm-kontron-bl.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 /dts-v1/;
8 #include "imx8mm-kontron-sl.dtsi"
12 compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
21 osc_can: clock-osc-can {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <16000000>;
25 clock-output-names = "osc-can";
29 compatible = "gpio-leds";
[all …]
H A Dimx8mm-kontron-bl-osm-s.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 /dts-v1/;
8 #include "imx8mm-kontron-osm-s.dtsi"
11 model = "Kontron BL i.MX8MM OSM-S (N802X S)";
12 compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm";
19 osc_can: clock-osc-can {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <40000000>;
23 clock-output-names = "osc-can";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Drenesas,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/renesas,rst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car and RZ/G Reset Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
16 - Latching of the levels on mode pins when PRESET# is negated,
17 - Mode monitoring register,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey970-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/pinctrl/hisi.h>
10 range: gpio-range {
11 #pinctrl-single,gpio-range-cells = <3>;
15 compatible = "pinctrl-single";
17 #pinctrl-cells = <1>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
21 /* pin base, nr pins & gpio function */
[all …]
H A Dhikey960-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/hisi.h>
12 range: gpio-range {
13 #pinctrl-single,gpio-range-cells = <3>;
17 compatible = "pinctrl-single";
19 #pinctrl-cells = <1>;
20 #gpio-range-cells = <0x3>;
21 pinctrl-single,register-width = <0x20>;
22 pinctrl-single,function-mask = <0x7>;
23 /* pin base, nr pins & gpio function */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dste-hrefv60plus.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2012 ST-Ericsson AB
6 #include "ste-href.dtsi"
9 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
10 compatible = "st-ericsson,hrefv60+", "st-ericsso
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8916-pins.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 blsp1_uart1_default: blsp1-uart1-default-state {
10 pins = "gpio0", "gpio1", "gpio2", "gpio3";
13 drive-strength = <16>;
14 bias-disable;
17 blsp1_uart1_sleep: blsp1-uart1-sleep-state {
18 pins = "gpio0", "gpio1", "gpio2", "gpio3";
21 drive-strength = <2>;
22 bias-pull-down;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/rockchip/
H A Drk3328-roc-pc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (c) 2021 T-Chip Intelligent Technology Co., Ltd
4 /dts-v1/;
6 #include <dt-bindings/input/input.h>
8 #include "rk3328-roc-cc.dts"
11 model = "Firefly ROC-RK3328-PC";
12 compatible = "firefly,roc-rk3328-pc", "rockchip,rk3328";
14 adc-keys {
15 compatible = "adc-keys";
16 io-channels = <&saradc 0>;
[all …]

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