Searched +full:pin10 +full:- +full:function (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Jean Delvare <jdelvare@suse.com>23 https://www.onsemi.com/pub/Collateral/ADT7473-D.PDF24 https://www.onsemi.com/pub/Collateral/ADT7475-D.PDF25 https://www.onsemi.com/pub/Collateral/ADT7476-D.PDF26 https://www.onsemi.com/pub/Collateral/ADT7490-D.PDF34 - adi,adt747335 - adi,adt7475[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>7 * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed8 * directly to pads on the SoC, others come from an 8-bit pcf857x IO12 * Lines which are routed to the 40-pin header are named as follows:15 * <pin#> is the actual pin number of the 40-pin header16 * <pin name> is the name of the pin by function/gpi[all...]