| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | cnxt,cx92755-pinctrl.txt | 1 Conexant Digicolor CX92755 General Purpose Pin Mapping
3 This document describes the device tree binding of the pin mapping hardware
7 === Pin Controller Node ===
11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
19 For example, the following is the bare minimum node:
22 compatible = "cnxt,cx92755-pinctrl";
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| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
15 used for a specific device or function. This node represents both mux and config
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
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| H A D | pinctrl-bindings.txt | 3 Hardware modules that control pin multiplexing or configuration parameters
4 such as pull-up/down, tri-state, drive-strength etc are designated as pin
5 controllers. Each pin controller must be represented as a node in device tree,
8 Hardware modules whose signals are affected by pin configuration are
10 node in device tree, just like any other hardware module.
12 For a client device to operate correctly, certain pin controllers must
13 set up certain specific pin configurations. Some client devices need a
14 single static pin configuration, e.g. set up during initialization. Others
15 need to reconfigure pins at run-time, for example to tri-state pins when the
21 for client device device tree nodes to map those state names to the pin
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| H A D | pinctrl-st.txt | 1 *ST pin controller.
3 Each multi-function pin is controlled, driven and routed through the
4 PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
6 the pin to different hardware blocks.
8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
12 gpio driver to configure a pin.
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
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| H A D | marvell,mvebu-pinctrl.txt | 3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
7 Please refer to pinctrl-bindings.txt in this directory for details of the
9 phrase "pin configuration node".
11 A Marvell SoC pin configuration node is a node of a group of pins which can
12 be used for a specific device or function. Each node requires one or more
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
19 Required properties for pin configuration node:
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
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| H A D | sprd,sc9860-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/sprd,sc9860-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SC9860 Pin Controller
10 - Baolin Wang <baolin.wang@linux.alibaba.com>
13 The Spreadtrum pin controller are organized in 3 blocks (types).
19 driving level": One pin can output 3.0v or 1.8v, depending on the
21 select 3.0v, then the pin can output 3.0v. "system control" is used
26 of them, so we can not make every Spreadtrum-special configuration
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| H A D | renesas,rzn1-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 Pin Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - const: renesas,r9a06g032-pinctrl # RZ/N1D
17 - const: renesas,rzn1-pinctrl # Generic RZ/N1
21 - description: GPIO Multiplexing Level1 Register Block
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| H A D | sunplus,sp7021-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Pin Controller
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
23 (1) function-group pins:
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| H A D | microchip,pic32-pinctrl.txt | 1 * Microchip PIC32 Pin Controller
3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
5 pin controller, GPIO, and interrupt bindings.
7 PIC32 'pin configuration node' is a node of a group of pins which can be
8 used for a specific device or function. This node represents configurations of
11 Required properties for pin controller node:
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
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| H A D | marvell,berlin2-soc-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/marvell,berlin2-soc-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Berlin pin-controller driver
10 - Antoine Tenart <atenart@kernel.org>
11 - Jisheng Zhang <jszhang@kernel.org>
14 Pin control registers are part of both chip controller and system controller
15 register sets. Pin controller nodes should be a sub-node of either the chip
16 controller or system controller node. The pins controlled are organized in
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| H A D | rockchip,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
18 Please refer to pinctrl-bindings.txt in this directory for details of the
20 phrase "pin configuration node".
22 The Rockchip pin configuration node is a node of a group of pins which can be
23 used for a specific device or function. This node represents both mux and
25 (also named pin mode) this pin can work on and the 'config' configures
26 various pad settings such as pull-up, etc.
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| H A D | pinctrl-vt8500.txt | 1 VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
3 These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
7 - compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9 - reg: Should contain the physical address of the module's registers.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 bit 0 - active low
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| H A D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
17 Specifies that the node is a GPIO controller
19 - ngpios:
23 - interrupts:
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| H A D | samsung,pinctrl-pins-cfg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
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| H A D | renesas,r9a09g077-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller.
14 Pin multiplexing and GPIO configuration are performed on a per-pin basis.
16 or alternate function mode. Each pin supports function mode values ranging from
22 - renesas,r9a09g077-pinctrl # RZ/T2H
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| H A D | ste,nomadik.txt | 4 - compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
5 "stericsson,stn8815-pinctrl"
6 - nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
7 (these have the register ranges used by the pin controller).
8 - prcm: phandle to the PRCMU managing the back end of this pin controller
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
16 pin, a group, or a list of pins or groups. This configuration can include the
17 mux function to select on those pin(s)/group(s), and various pin configuration
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| H A D | samsung,pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
15 This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
18 All the pin controller nodes should be represented in the aliases node using
22 - External GPIO interrupts (see interrupts property in pin controller node);
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| H A D | fsl,imx27-pinctrl.txt | 4 - compatible: "fsl,imx27-iomuxc"
6 The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
8 Required properties for pin configuration node:
9 - fsl,pins: three integers array, represents a group of pins mux and config
10 setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
12 PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
13 configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
19 function value is used to select the pin function.
21 0 - Primary function
22 1 - Alternate function
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| H A D | nxp,lpc1850-scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nxp,lpc1850-scu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP LPC18xx/43xx SCU pin controller
10 Not all pins support all pin generic node properties so either refer to
11 the NXP 1850/4350 user manual or the pin table in the pinctrl-lpc18xx
12 driver for supported pin properties.
15 - Frank Li <Frank.Li@nxp.com>
19 const: nxp,lpc1850-scu
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| /linux/drivers/pinctrl/ |
| H A D | core.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
31 * @node: node to include this pin controller in the global pin controller list
32 * @desc: the pin controller descriptor supplied when initializing this pin
34 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
36 * @pin_group_tree: optionally each pin group can be stored in this radix tree
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| H A D | core.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
51 /* Global list of pin control devices (struct pinctrl_dev) */
54 /* List of pin controller handles (struct pinctrl) */
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
78 return pctldev->desc->name; in pinctrl_dev_get_name()
84 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
90 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
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| /linux/drivers/pinctrl/sunxi/ |
| H A D | pinctrl-sunxi.c | 6 * Maxime Ripard <maxime.ripard@free-electrons.com>
28 #include <linux/pinctrl/pinconf-generic.h>
33 #include <dt-bindings/pinctrl/sun4i-a10.h>
36 #include "pinctrl-sunxi.h"
51 * - Mux config
52 * - Data value
53 * - Drive level
54 * - Pull direction
59 * They take a pin number which is relative to the start of the current device.
66 static u32 sunxi_bank_offset(const struct sunxi_pinctrl *pctl, u32 pin) in sunxi_bank_offset() argument
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| /linux/arch/sparc/kernel/ |
| H A D | pcic.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * pcic.c: MicroSPARC-IIep PCI controller support
11 * CP-1200 by Eric Brower.
49 * schematics. And this actually sucks. -- zaitcev 1999/05/12
56 * find PCIC pin number where INT line goes. Then we may either program
62 unsigned char pin; /* PCIC external interrupt pin */ member
74 * JavaEngine-1 apparently has different versions.
76 * According to communications with Sun folks, for P2 build 501-4628-03:
77 * pin 0 - parallel, audio;
78 * pin 1 - Ethernet;
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| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | as3722.txt | 4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
18 - ams,enable-internal-int-pullup: Boolean property, to enable internal pullup on
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| /linux/Documentation/devicetree/bindings/soc/ti/ |
| H A D | wkup-m3-ipc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dave Gerlach <d-gerlach@ti.com>
11 - Drew Fustini <dfustini@baylibre.com>
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
22 Wkup M3 Device Node
24 A wkup_m3_ipc device node is used to represent the IPC registers within an
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