| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | marvell,armada-37xx-pinctrl.txt | 1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
18 of the phrase "pin configuration node".
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
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| H A D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
18 a group of pins, and only affects those parameters that are explicitly listed.
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| H A D | cnxt,cx92755-pinctrl.txt | 1 Conexant Digicolor CX92755 General Purpose Pin Mapping
3 This document describes the device tree binding of the pin mapping hardware
7 === Pin Controller Node ===
11 - compatible: Must be "cnxt,cx92755-pinctrl"
12 - reg: Base address of the General Purpose Pin Mapping register block and the
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells: Must be <2>. The first cell is the pin number and the
16 second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
22 compatible = "cnxt,cx92755-pinctrl";
24 gpio-controller;
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| H A D | brcm,bcm11351-pinctrl.txt | 1 Broadcom BCM281xx Pin Controller
3 This is a pin controller for the Broadcom BCM281xx SoC family, which includes
6 === Pin Controller Node ===
10 - compatible: Must be "brcm,bcm11351-pinctrl"
11 - reg: Base address of the PAD Controller register block and the size
17 compatible = "brcm,bcm11351-pinctrl";
21 As a pin controller device, in addition to the required properties, this node
22 should also contain the pin configuration nodes that client devices reference,
25 === Pin Configuration Node ===
27 Each pin configuration node is a sub-node of the pin controller node and is a
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| H A D | nvidia,tegra194-pinmux.txt | 4 - compatible: "nvidia,tegra194-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
11 phrase "pin configuration node".
13 Tegra's pin configuration nodes act as a container for an arbitrary number of
15 pin, a group, or a list of pins or groups. This configuration can include the
16 mux function to select on those pin(s)/group(s), and various pin configuration
17 parameters, such as pull-up, tristate, drive strength, etc.
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| H A D | pinmux-node.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Multiplexing Node
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
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| H A D | fsl,imx-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'mux' selects the function mode(also named mux
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
25 - fsl,pins: each entry consists of 6 integers and represents the mux and config
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| H A D | lantiq,pinctrl-falcon.txt | 4 - compatible: "lantiq,pinctrl-falcon"
5 - reg: Should contain the physical address and length of the gpio/pinmux
8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 Lantiq's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those group(s), and two pin configuration parameters:
16 pull-up and open-drain
22 other words, a subnode that lists a mux function but no pin configuration
23 parameters implies no information about any pin configuration parameters.
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| H A D | atmel,at91-pinctrl.txt | 10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
23 or "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl"
24 - atmel,mux-mask: array of mask (periph per bank) to describe if a pin can be
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| H A D | nvidia,tegra210-pinmux.txt | 4 - compatible: "nvidia,tegra210-pinmux"
5 - reg: Should contain a list of base address and size pairs for:
6 - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7 - second entry: The PINMUX_AUX_* registers (pinmux)
9 Please refer to pinctrl-bindings.txt in this directory for details of the
11 phrase "pin configuration node".
13 Tegra's pin configuration nodes act as a container for an arbitrary number of
15 pin, a group, or a list of pins or groups. This configuration can include the
16 mux function to select on those pin(s)/group(s), and various pin configuration
17 parameters, such as pull-up, tristate, drive strength, etc.
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| H A D | renesas,pfc-pinctrl.txt | 1 * Renesas Pin Function Controller (GPIO and Pin Mux/Config)
3 The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0,
7 Pin Control
8 -----------
12 - compatible: should be one of the following.
13 - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller.
14 - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller.
15 - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller.
16 - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller.
17 - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller.
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| H A D | pinctrl-mt7622.txt | 4 - compatible: Should be one of the following
5 "mediatek,mt7622-pinctrl" for MT7622 SoC
6 "mediatek,mt7629-pinctrl" for MT7629 SoC
7 - reg: offset and length of the pinctrl space
9 - gpio-controller: Marks the device node as a GPIO controller.
10 - #gpio-cells: Should be two. The first cell is the pin number and the
14 - interrupt-controller : Marks the device node as an interrupt controller
16 If the property interrupt-controller is defined, following property is required
17 - reg-names: A string describing the "reg" entries. Must contain "eint".
18 - interrupts : The interrupt output from the controller.
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| H A D | nxp,s32g2-siul2-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/nxp,s32g2-siul
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| H A D | nvidia,tegra20-pinmux.txt | 4 - compatible: "nvidia,tegra20-pinmux"
5 - reg: Should contain the register physical address and length for each of
6 the tri-state, mux, pull-up/down, and pad control register sets.
8 Please refer to pinctrl-bindings.txt in this directory for details of the
10 phrase "pin configuration node".
12 Tegra's pin configuration nodes act as a container for an arbitrary number of
14 pin, a group, or a list of pins or groups. This configuration can include the
15 mux function to select on those pin(s)/group(s), and various pin configuration
16 parameters, such as pull-up, tristate, drive strength, etc.
22 other words, a subnode that lists a mux function but no pin configuration
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| H A D | nvidia,tegra-pinmux-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
16 the phrase "pin configuration node".
18 Tegra's pin configuration nodes act as a container for an arbitrary number
20 for a pin, a group, or a list of pins or groups. This configuration can
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| H A D | abilis,tb10x-iomux.txt | 1 Abilis Systems TB10x pin controller
5 -------------------
7 - compatible: should be "abilis,tb10x-iomux";
8 - reg: should contain the physical address and size of the pin controller's
13 --------------------
15 Functions are defined (and referenced) by sub-nodes of the pin controller.
16 Every sub-node defines exactly one function (implying a set of pins).
17 Every function is associated to one named pin group inside the pin controller
18 driver and these names are used to associate pin group predefinitions to pin
19 controller sub-nodes.
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| H A D | marvell,mvebu-pinctrl.txt | 3 The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
7 Please refer to pinctrl-bindings.txt in this directory for details of the
9 phrase "pin configuration node".
11 A Marvell SoC pin configuration node is a node of a group of pins which can
13 mpp pins or group of pins and a mpp function common to all pins.
16 - compatible: "marvell,<soc>-pinctrl"
17 Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
19 Required properties for pin configuration node:
20 - marvell,pins: string array of mpp pins or group of pins to be muxed.
21 - marvell,function: string representing a function to mux to for all
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| H A D | lantiq,pinctrl-xway.txt | 4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
15 phrase "pin configuration node".
17 Lantiq's pin configuration nodes act as a container for an arbitrary number of
19 pin, a group, or a list of pins or groups. This configuration can include the
20 mux function to select on those group(s), and two pin configuration parameters:
21 pull-up and open-drain
27 other words, a subnode that lists a mux function but no pin configuration
28 parameters implies no information about any pin configuration parameters.
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| H A D | berlin,pinctrl.txt | 1 * Pin-controller driver for the Marvell Berlin SoCs
3 Pin control registers are part of both chip controller and system
4 controller register sets. Pin controller nodes should be a sub-node of
6 controlled are organized in groups, so no actual pin information is
9 A pin-controller node should contain subnodes representing the pin group
10 configurations, one per function. Each subnode has the group name and
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
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| /freebsd/sys/contrib/device-tree/src/mips/mobileye/ |
| H A D | eyeq6h-pins.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
9 * [0] | MUX_SEL | 0 - GPIO, 1 - alternative func
14 * [13:12] | PUD | pull-up/pull-down. 0, 3 - no, 1 - PD, 2 - PU
20 // TODO: use pinctrl-single,bias-pullup
21 // TODO: use pinctrl-single,bias-pulldown
22 // TODO: use pinctrl-single,drive-strength
23 // TODO: use pinctrl-single,input-schmitt
25 i2c0_pins: i2c0-pins {
26 pinctrl-single,pins = <
27 0x000 0x200 // I2C0_SCL pin
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| /freebsd/sys/dev/ftgpio/ |
| H A D | ftgpio.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2016-2023 Stormshield
48 #define GPIO_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
50 #define GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx)
51 #define GPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
52 #define GPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
53 #define GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED)
54 #define GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED)
118 ftgpio_group_get_ioreg(struct ftgpio_softc *sc, uint8_t reg, unsigned group) in ftgpio_group_get_ioreg() argument
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| /freebsd/sys/dev/p2sb/ |
| H A D | lewisburg_gpiocm.c | 1 /*-
54 #define LBGGPIOCM_READ(sc, reg) p2sb_port_read_4(sc->p2sb, sc->port, reg)
56 p2sb_port_write_4(sc->p2sb, sc->port, reg, val)
57 #define LBGGPIOCM_LOCK(sc) p2sb_lock(sc->p2sb)
58 #define LBGGPIOCM_UNLOCK(sc) p2sb_unlock(sc->p2sb)
107 for (i = 0; i < sc->community->ngroups; ++i) in lbggpiocm_get_group()
108 if (sc->community->groups[i].dev == child) in lbggpiocm_get_group()
109 return (&sc->community->groups[i]); in lbggpiocm_get_group()
115 lbggpiocm_getpad(struct lbggpiocm_softc *sc, uint32_t pin) in lbggpiocm_getpad() argument
118 if (pin >= sc->community->npins) in lbggpiocm_getpad()
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| /freebsd/contrib/wpa/wpa_supplicant/ |
| H A D | README-P2P | 1 wpa_supplicant and Wi-Fi P2P
4 This document describes how the Wi-Fi P2P implementation in
10 Introduction to Wi-Fi P2P
11 -------------------------
15 More information about Wi-Fi P2P is available from Wi-Fi Alliance:
16 http://www.wi-fi.org/Wi-Fi_Direct.php
20 -----------------------------
26 ----------------------------
28 Wi-Fi P2P is an optional component that needs to be enabled in the
30 configuration that includes Wi-Fi P2P support and Linux nl80211
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| /freebsd/contrib/wpa/wpa_supplicant/examples/p2p/ |
| H A D | p2p_connect.py | 4 # and form a group
17 print(" %s -i <interface_name> -m <wps_method> \ " \
19 print(" -a <addr> [-p <pin>] [-g <go_intent>] \ ")
20 print(" [-w <wpas_dbus_interface>]")
22 print(" -i = interface name")
23 print(" -m = wps method")
24 print(" -a = peer address")
25 print(" -p = pin number (8 digits)")
26 print(" -g = group owner intent")
27 print(" -w = wpas dbus interface = fi.w1.wpa_supplicant1")
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| /freebsd/sys/dev/nctgpio/ |
| H A D | nctgpio.c | 1 /*-
51 #define NCT_PPOD_LDN 0xf /* LDN used to select Push-Pull/Open-Drain */
54 #define NCT_IO_GSR 0 /* Group Select */
63 #define NCT_PIN_IS_VALID(_sc, _p) ((_p) < (_sc)->npins)
64 #define NCT_PIN_GROUP(_sc, _p) ((_sc)->pinmap[(_p)].group)
65 #define NCT_PIN_GRPNUM(_sc, _p) ((_sc)->pinmap[(_p)].grpnum)
66 #define NCT_PIN_BIT(_sc, _p) ((_sc)->pinmap[(_p)].bit)
98 uint8_t ppod_reg; /* Push-Pull/Open-Drain */
123 struct nct_gpio_group *group; member
130 #define GPIO_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
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