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Searched +full:pic32mzda +full:- +full:gpio (Results 1 – 8 of 8) sorted by relevance

/linux/arch/mips/boot/dts/pic32/
H A Dpic32mzda.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/microchip,pic32-clock.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&evic>;
33 #address-cells = <1>;
34 #size-cells = <0>;
43 compatible = "microchip,pic32mzda-infra";
49 #clock-cells = <0>;
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H A Dpic32mzda_sk.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "pic32mzda.dtsi"
14 compatible = "microchip,pic32mzda-sk", "microchip,pic32mzda";
15 model = "Microchip PIC32MZDA Starter Kit";
27 compatible = "gpio-leds";
28 pinctrl-names = "default";
29 pinctrl-0 = <&user_leds_s0>;
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/linux/Documentation/devicetree/bindings/gpio/
H A Dmicrochip,pic32mzda-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/microchip,pic32mzda-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PIC32 GPIO controller
10 - Joshua Henderson <joshua.henderson@microchip.com>
11 - Purna Chandra Mandal <purna.mandal@microchip.com>
15 const: microchip,pic32mzda-gpio
20 gpio-controller: true
22 gpio-ranges: true
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,pic32-pinctrl.txt3 Please refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
4 ../interrupt-controller/interrupts.txt for generic information regarding
5 pin controller, GPIO, and interrupt bindings.
12 - compatible: "microchip,pic32mada-pinctrl"
13 - reg: Address range of the pinctrl registers.
14 - clocks: Clock specifier (see clock bindings for details)
16 Required properties for pin configuration sub-nodes:
17 - pins: List of pins to which the configuration applies.
19 Optional properties for pin configuration sub-nodes:
20 ----------------------------------------------------
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/linux/Documentation/devicetree/bindings/spi/
H A Dmicrochip,spi-pic32.txt4 - compatible: Should be "microchip,pic32mzda-spi".
5 - reg: Address and length of register space for the device.
6 - interrupts: Should contain all three spi interrupts in sequence
7 of <fault-irq>, <receive-irq>, <transmit-irq>.
8 - interrupt-names: Should be "fault", "rx", "tx" in order.
9 - clocks: Phandle of the clock generating SPI clock on the bus.
10 - clock-names: Should be "mck0".
11 - cs-gpios: Specifies the gpio pins to be used for chipselects.
12 See: Documentation/devicetree/bindings/spi/spi-bus.txt
15 - dmas: Two or more DMA channel specifiers following the convention outlined
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/linux/drivers/pinctrl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 bool "AMD GPIO pin control"
44 The driver for memory mapped GPIO functionality on AMD platforms
47 for GPIO use.
53 tristate "AMDISP GPIO pin control"
60 The driver for memory mapped GPIO functionality on AMD platforms
67 tristate "Apple SoC GPIO pin controller driver"
76 This is the driver for the GPIO controller found on Apple ARM SoCs,
80 will be called pinctrl-apple-gpio.
83 bool "Axis ARTPEC-6 pin controller driver"
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H A Dpinctrl-pic32.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/gpio/driver.h>
15 #include <linux/pinctrl/pinconf-generic.h>
23 #include <asm/mach-pic32/pic32.h>
25 #include "pinctrl-utils.h"
26 #include "pinctrl-pic32.h"
1702 return &pctl->gpio_banks[pin / PINS_PER_BANK]; in pctl_to_bank()
1709 return pctl->ngroups; in pic32_pinctrl_get_groups_count()
1717 return pctl->groups[group].name; in pic32_pinctrl_get_group_name()
1727 *pins = &pctl->groups[group].pin; in pic32_pinctrl_get_group_pins()
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/linux/drivers/tty/serial/
H A Dpic32_uart.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
11 #include <linux/gpio/consumer.h>
26 #include <asm/mach-pic32/pic32.h>
29 #define PIC32_DEV_NAME "pic32-uart"
43 /* struct pic32_sport - pic32 serial port descriptor
52 * @cts_gpiod: clear to send GPIO
82 __raw_writel(val, sport->port.membase + reg); in pic32_uart_writel()
87 return __raw_readl(sport->port.membase + reg); in pic32_uart_readl()
166 if (!sport->cts_gpiod) in pic32_uart_get_mctrl()
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