pic\-base\-vec (full) in projects: freebsd

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Searched +full:pic +full:- +full:base +full:- +full:vec (Results 1 – 25 of 33) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A D	loongson,pch-pic.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Loongson PCH PIC Controller 10 - Jiaxun Yang <jiaxun.yang@flygoat.com> 14 transforming interrupts from on-chip devices into HyperTransport vectorized 19 const: loongson,pch-pic-1.0 24 loongson,pic-base-vec: 26 u32 value of the base of parent HyperTransport vector allocated [all …]`
/freebsd/sys/contrib/device-tree/src/loongarch/
H A D	loongson-2k2000.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/clock/loongson,ls2k-clk.h> 12 #address-cells = <2>; 13 #size-cells = <2>; 16 #address-cells = <1>; 17 #size-cells = <0>; 34 ref_100m: clock-ref-100m { 35 compatible = "fixed-clock"; [all …]`
/freebsd/sys/contrib/device-tree/src/mips/loongson/
H A D	ls7a-pch.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 5 compatible = "simple-bus"; 6 #address-cells = <2>; 7 #size-cells = <2>; 13 pic: interrupt-controller@10000000 { label 14 compatible = "loongson,pch-pic [all...]`
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A D	HexagonISelLowering.h	1 //===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 39 ADDC, // Add with carry: (X, Y, Cin) -> (X+Y, Cout). 40 SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout). 83 D2P, // Convert 8-byte value to 8-bit predicate register. [] 84 P2D, // Convert 8-bit predicate register to 8-byte value. [] 95 TL_TRUNCATE, // from auto-folding operations, e.g. 111 TYPECAST, // No-op that's used to convert between different legal [all …]
H A D	HexagonISelLowering.cpp	`1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===// 5 // SPDX-License-Identifie 628 getPostIndexedAddressParts(SDNode * N,SDNode * Op,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const getPostIndexedAddressParts() argument 3061 SDValue Vec = Op.getOperand(0); LowerEXTRACT_VECTOR_ELT() local 3216 SDValue Base = LN->getBasePtr(); LowerUnalignedLoad() local [all...]`
/freebsd/sys/x86/x86/
H A D	io_apic.c	`1 /- 2 SPDX-License-Identifier: BSD-2-Clause 69 * We assume that IRQs 1 - 15 behave like ISA IRQs and that all other 94 struct pic io_pic; 98 u_int io_intbase:8; /* System Interrupt base / 114 static void ioapic_register_sources(struct pic pic); 124 static void ioapic_resume(struct pic pic, bool suspend_cancelled); 130 struct pic ioapic_template = { 165 if (src->io_edgetrigger) in _ioapic_eoi_source() 167 io = (struct ioapic )isrc->is_pic; in _ioapic_eoi_source() [all …]`
H A D	local_apic.c	`1 /- 2 SPDX-License-Identifier: BSD-3-Clause 15 * 3. Neither the name of the author nor the names of any co-contributors 98 * I/O interrupts use non-negative IRQ values. These values are used 99 * to mark unused IDT entries or IDT entries reserved for a non-I/O 102 #define IRQ_FREE -1 103 #define IRQ_TIMER -2 104 #define IRQ_SYSCALL -3 105 #define IRQ_DTRACE_RET -4 106 #define IRQ_EVTCHN -5 [all …]`
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A D	VPlanRecipes.cpp	1 //===- VPlanRecipes.cpp - Implementations for VPlan recipes ---------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 44 #define LV_NAME "loop-vectorize" 50 return cast<VPInterleaveRecipe>(this)->getNumStoreOperands() > 0; in mayWriteToMemory() 55 return cast<Instruction>(getVPSingleValue()->getUnderlyingValue()) in mayWriteToMemory() 56 ->mayWriteToMemory(); in mayWriteToMemory() 59 ->getCalledScalarFunction() in mayWriteToMemory() 60 ->onlyReadsMemory(); in mayWriteToMemory() [all …]
/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A D	CommonArgs.cpp	1 //===--- CommonArgs.cpp - Args handling for multiple toolchains -- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 50 #include "llvm/Config/llvm-config.h" 176 // True if a target-specific option requires the frame chain to be preserved, 181 // For 32-bit Arm, the -mframe-chain=aapcs and -mframe-chain=aapcs+leaf in mustMaintainValidFrameChain() 183 // new AAPCS-compilant frame record), even with -fno-omit-frame-pointer. in mustMaintainValidFrameChain() 185 StringRef V = A->getValue(); in mustMaintainValidFrameChain() 193 // True if a target-specific option causes -fno-omit-frame-pointer to also 198 // For 32-bit Arm, the -mframe-chain=aapcs+leaf option causes the in framePointerImpliesLeafFramePointer() [all …]
H A D	Clang.cpp	1 //===-- Clang.cpp - Clang+LLVM ToolChain Implementations --------- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 47 #include "llvm/Config/llvm-config.h" 81 << A->getBaseArg().getAsString(Args) in CheckPreprocessingOptions() 82 << (D.IsCLMode() ? "/E, /P or /EP" : "-E"); in CheckPreprocessingOptions() 92 D.Diag(diag::err_drv_argument_not_allowed_with) << A->getAsString(Args) in CheckCodeGenerationOptions() 93 << "-static"; in CheckCodeGenerationOptions() 97 // This is used for the space-separated argument list specified with 98 // the -dwarf-debug-flags option. [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A D	VEISelLowering.cpp	1 //===-- VEISelLowering.cpp - VE DAG Lowering Implementation ---------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 39 #define DEBUG_TYPE "ve-lower" 41 //===----------------------------------------------------------------------===// 43 //===----------------------------------------------------------------------===// 91 if (Subtarget->enableVPU()) { in initRegisterClasses() 212 // VE doesn't have instructions for fp<->uint, so expand them by llvm in initSPUActions() 225 /// Floating-point Ops { in initSPUActions() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A D	MipsSEISelDAGToDAG.cpp	1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 38 #define DEBUG_TYPE "mips-isel" 42 if (Subtarget->inMips16Mode()) in runOnMachineFunction() 79 uint64_t RegNum = RegIdx->getAsZExtVal(); in getMSACtrlReg() 106 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), in replaceUsesWithZeroReg() 107 E = MRI->use_end(); U != E;) { in replaceUsesWithZeroReg() 114 if (MI->isPHI() \|\| MI->isRegTiedToDefOperand(OpNo) \|\| MI->isPseudo()) in replaceUsesWithZeroReg() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVISelLowering.cpp	1 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation ------ 3475 SDValue Vec = SplatVal.getOperand(0); matchSplatAsGather() local 3568 SDValue Vec = DAG.getSplatBuildVector(VT, DL, DominantValue); lowerBuildVectorViaDominantValues() local 3689 SDValue Vec = DAG.getBuildVector(IntegerViaVecVT, DL, Elts); lowerBuildVectorOfConstants() local 3811 SDValue Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ViaVecVT, lowerBuildVectorOfConstants() local 4086 SDValue Vec = DAG.getUNDEF(ContainerVT); lowerBUILD_VECTOR() local 4198 SDValue Vec; lowerBUILD_VECTOR() local 4756 __anon765c18b70c02(ArrayRef<int> Mask, unsigned Base, int Offset) lowerVECTOR_SHUFFLEAsVSlide1() argument 4782 auto Vec = DAG.getNode(OpCode, DL, ContainerVT, lowerVECTOR_SHUFFLEAsVSlide1() local 5053 SDValue Vec = DAG.getUNDEF(ContainerVT); lowerShuffleViaVRegSplitting() local 6894 SDValue Vec = DAG.getUNDEF(VT); LowerOperation() local 8448 SDValue Vec = Op.getOperand(0); lowerINSERT_VECTOR_ELT() local 8616 SDValue Vec = Op.getOperand(0); lowerEXTRACT_VECTOR_ELT() local 8839 SDValue Vec = DAG.getBitcast(I32VT, Operands[2]); lowerVectorIntrinsicScalars() local 9247 SDValue Vec = Op.getOperand(1); LowerINTRINSIC_WO_CHAIN() local 9713 SDValue Vec = Op.getOperand(IsVP ? 1 : 0); lowerVectorMaskVecReduction() local 9801 lowerReductionSeq(unsigned RVVOpcode,MVT ResVT,SDValue StartValue,SDValue Vec,SDValue Mask,SDValue VL,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerReductionSeq() argument 9833 SDValue Vec = Op.getOperand(0); lowerVECREDUCE() local 9964 SDValue Vec = Op.getOperand(1); lowerVPREDUCE() local 10011 SDValue Vec = Op.getOperand(0); lowerINSERT_SUBVECTOR() local 10248 SDValue Vec = Op.getOperand(0); lowerEXTRACT_SUBVECTOR() local 12663 SDValue Vec = N->getOperand(0); ReplaceNodeResults() local 12853 SDValue Vec = N->getOperand(1); ReplaceNodeResults() local 13006 SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec, combineBinOpOfExtractToReduceTree() local 13028 SDValue Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ReduceVT, SrcVec, combineBinOpOfExtractToReduceTree() local 17530 SDValue Vec = N->getOperand(0); PerformDAGCombine() local 17553 SDValue Base = N->getOperand(3); PerformDAGCombine() local 17571 SDValue Base = N->getOperand(3); PerformDAGCombine() local 21185 getIndexedAddressParts(SDNode * Op,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const getIndexedAddressParts() argument 21221 getPreIndexedAddressParts(SDNode * N,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const getPreIndexedAddressParts() argument 21244 getPostIndexedAddressParts(SDNode * N,SDNode * Op,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const getPostIndexedAddressParts() argument [all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A D	CommandFlags.cpp	1 //===-- CommandFlags.cpp - Command Line Flags Interface ---------- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file contains codegen-specific flags that are shared between different 13 //===----------------------------------------------------------------------===// 50 if (NAME##View->getNumOccurrences()) { \ 121 "march", cl::desc("Architecture to generate code for (see --version)")); in CGOPT() 125 "mcpu", cl::desc("Target a specific cpu type (-mcpu=help for details)"), in CGOPT() 126 cl::value_desc("cpu-name"), cl::init("")); in CGOPT() 131 cl::desc("Target specific attributes (-mattr=help for details)"), in CGOPT() [all …]
H A D	TargetLoweringObjectFileImpl.cpp	1 //===- llvm/CodeGen/TargetLoweringObjectFileImpl.cpp - Object File Info ---===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 76 "jumptable-in-function-section", cl::Hidden, cl::init(false), 89 StringRef Key = MFE.Key->getString(); in GetObjCImageInfo() 90 if (Key == "Objective-C Image Info Version") { in GetObjCImageInfo() 91 Version = mdconst::extract<ConstantInt>(MFE.Val)->getZExtValue(); in GetObjCImageInfo() 92 } else if (Key == "Objective-C Garbage Collection" \|\| in GetObjCImageInfo() 93 Key == "Objective-C GC Only" \|\| in GetObjCImageInfo() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A D	X86ISelLowering.cpp	1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 71 #define DEBUG_TYPE "x86-isel" 74 "x86-experimental-pref-innermost-loop-alignment", cl::init(4), 78 "alignment set by x86-experimental-pref-loop-alignment."), 82 "x86-br-merging-base-cost", cl::init(2), 88 "will be merged, and above which conditionals will be split. Set to -1 " 93 "x86-br-merging-ccmp-bias", cl::init(6), [all …]
H A D	X86ISelDAGToDAG.cpp	1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 23 #include "llvm/Config/llvm-config.h" 39 #define DEBUG_TYPE "x86-isel" 40 #define PASS_NAME "X86 DAG->DAG Instruction Selection" 44 static cl::opt<bool> AndImmShrink("x86-and-imm-shrink", cl::init(true), 49 "x86-promote-anyext-load", cl::init(true), 54 //===----------------------------------------------------------------------===// [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A D	WebAssemblyISelLowering.cpp	1 //=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 44 #define DEBUG_TYPE "wasm-lower" 49 auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32; in WebAssemblyTargetLowering() 59 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering() 65 if (Subtarget->hasSIMD128()) { in WebAssemblyTargetLowering() 73 if (Subtarget->hasHalfPrecision()) { in WebAssemblyTargetLowering() 76 if (Subtarget->hasReferenceTypes()) { in WebAssemblyTargetLowering() [all …]
/freebsd/contrib/elftoolchain/readelf/
H A D	readelf.c	`1 /- 2 Copyright (c) 2009-2015 Kai Wang 57 ELFTC_VCSID("$Id: readelf.c 3769 2019-06-29 15:15:02Z emaste $"); 192 {"arch-specific", no_argument, NULL, 'A'}, 193 {"archive-index", no_argument, NULL, 'c'}, 194 {"debug-dump", optional_argument, NULL, OPTION_DEBUG_DUMP}, 197 {"file-header", no_argument, NULL, 'h'}, 198 {"full-section-name", no_argument, NULL, 'N'}, 201 {"hex-dump", required_argument, NULL, 'x'}, 204 {"program-headers", no_argument, NULL, 'l'}, [all …]`
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A D	AArch64ISelLowering.cpp	1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 109 #define DEBUG_TYPE "aarch64-lower" 119 "aarch64-elf-ldtls-generation", cl::Hidden, 124 EnableOptimizeLogicalImm("aarch64-enable-logical-imm", cl::Hidden, 134 EnableCombineMGatherIntrinsics("aarch64-enable-mgather-combine", cl::Hidden, 139 static cl::opt<bool> EnableExtToTBL("aarch64-enable-ext-to-tbl", cl::Hidden, 146 static cl::opt<unsigned> MaxXors("aarch64-max-xors", cl::init(16), cl::Hidden, [all …]
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A D	AutoUpgrade.cpp	1 //===-- AutoUpgrade.cpp - Implement auto-upgrade helper functions ---------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file implements the auto-upgrade helper functions. 13 //===----------------------------------------------------------------------===// 49 DisableAutoUpgradeDebugInfo("disable-auto-upgrade-debug-info", 52 static void rename(GlobalValue GV) { GV->setName(GV->getName() + ".old"); } in rename() 60 Type Arg0Type = F->getFunctionType()->getParamType(0); in upgradePTESTIntrinsic() 61 if (Arg0Type != FixedVectorType::get(Type::getFloatTy(F->getContext()), 4)) in upgradePTESTIntrinsic() 66 NewFn = Intrinsic::getDeclaration(F->getParent(), IID); in upgradePTESTIntrinsic() [all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A D	LegalizeDAG.cpp	1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 62 /// Keeps track of state when getting the sign of a floating-point value as an 76 //===----------------------------------------------------------------------===// 126 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 210 UpdatedNodes->insert(N); in ReplacedNode() 214 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode() 215 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A D	SparcISelLowering.cpp	1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===// 40 //===----------------------------------------------------------------------===// 42 //===----------------------------------------------------------------------===// 106 // Allocate a full-sized argument for the 64-bit ABI. 112 "Can't handle non-64 bits locations"); in Analyze_CC_Sparc64_Full() 121 // Promote integers to %i0-%i5. in Analyze_CC_Sparc64_Full() 124 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). in Analyze_CC_Sparc64_Full() [all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A D	BasicTTIImpl.h	1 //===- BasicTTIImpl.h -------------------------------------------- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 /// terms of the target-independent code generator and TargetLowering 14 //===----------------------------------------------------------------------===// 71 /// Base class which can be used to help build a TTI implementation. 96 Cost += thisT()->getVectorInstrCost(Instruction::ExtractElement, VTy, in getBroadcastShuffleOverhead() 99 for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { in getBroadcastShuffleOverhead() 100 Cost += thisT()->getVectorInstrCost(Instruction::InsertElement, VTy, in getBroadcastShuffleOverhead() 118 for (int i = 0, e = VTy->getNumElements(); i < e; ++i) { in getPermuteShuffleOverhead() [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A D	PPCISelLowering.cpp	1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 106 #define DEBUG_TYPE "ppc-lowering" 108 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc", 111 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref", 114 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned", 117 static cl::opt<bool> DisableSCO("disable-ppc-sco", 120 static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32", [all …]