/linux/arch/arm64/boot/dts/freescale/ |
H A D | fsl-ls2088a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 12 /dts-v1/; 14 #include "fsl-ls2088a.dtsi" 15 #include "fsl-ls208xa-rdb.dtsi" 19 compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; 22 stdout-path = "serial1:115200n8"; 27 phy-handle = <&mdio1_phy1>; 28 phy-connection-type = "10gbase-r"; 32 phy-handle = <&mdio1_phy2>; 33 phy-connection-type = "10gbase-r"; [all …]
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H A D | fsl-ls1088a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Copyright 2017-2020 NXP 11 /dts-v1/; 13 #include "fsl-ls1088a.dtsi" 17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; 21 phy-handle = <&mdio2_aquantia_phy>; 22 phy-connection-type = "10gbase-r"; 23 pcs-handle = <&pcs2>; 27 phy-handle = <&mdio1_phy5>; 28 phy-connection-type = "qsgmii"; [all …]
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H A D | fsl-lx2162a-clearfog.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 5 // Copyright 2023 Josua Mayer <josua@solid-run.com> 7 /dts-v1/; 9 #include "fsl-lx2160a.dtsi" 10 #include "fsl-lx2162a-sr-som.dtsi" 14 compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a"; 35 stdout-path = "serial0:115200n8"; 39 compatible = "gpio-leds"; 41 led_sfp_at: led-sfp-at { 43 default-state = "off"; [all …]
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H A D | fsl-ls1043a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 11 /dts-v1/; 12 #include "fsl-ls1043a.dtsi" 16 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a"; 26 stdout-path = "serial0:115200n8"; 36 shunt-resistor = <1000>; 67 #address-cells = <2>; 68 #size-cells = <1>; [all …]
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H A D | fsl-ls1088a-ten64.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 * Based on fsl-ls1088a-rdb.dts 5 * Copyright 2017-2020 NXP 6 * Copyright 2019-2021 Traverse Technologies 11 /dts-v1/; 13 #include "fsl-ls1088a.dtsi" 15 #include <dt-bindings/gpio/gpio.h> 16 #include <dt-bindings/input/input.h> 28 stdout-path = "serial0:115200n8"; 32 compatible = "gpio-keys"; [all …]
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H A D | fsl-ls2080a-rdb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 13 /dts-v1/; 15 #include "fsl-ls2080a.dtsi" 16 #include "fsl-ls208xa-rdb.dtsi" 17 #include <dt-bindings/interrupt-controller/arm-gic.h> 21 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; 24 stdout-path = "serial1:115200n8"; 29 phy-handle = <&mdio2_phy1>; 30 phy-connection-type = "10gbase-r"; 34 phy-handle = <&mdio2_phy2>; [all …]
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/linux/drivers/phy/mediatek/ |
H A D | phy-mtk-mipi-csi-0-5.c | 1 // SPDX-License-Identifier: GPL-2.0 9 #include <dt-bindings/phy/phy.h> 15 #include <linux/phy/phy.h> 19 #include "phy-mtk-io.h" 20 #include "phy-mtk-mipi-csi-0-5-rx-reg.h" 27 struct phy *phy; member 28 u32 type; member 73 static int mtk_mipi_phy_power_on(struct phy *phy) in mtk_mipi_phy_power_on() argument 75 struct mtk_mipi_cdphy_port *port = phy_get_drvdata(phy); in mtk_mipi_phy_power_on() 76 void __iomem *base = port->base; in mtk_mipi_phy_power_on() [all …]
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H A D | phy-mtk-xsphy.c | 1 // SPDX-License-Identifier: GPL-2.0 10 #include <dt-bindings/phy/phy.h> 16 #include <linux/phy/phy.h> 19 #include "phy-mtk-io.h" 21 /* u2 phy banks */ 26 /* u3 phy shared banks */ 30 /* u3 phy banks */ 85 struct phy *phy; member 87 struct clk *ref_clk; /* reference clock of anolog phy */ 89 u32 type; member [all …]
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/linux/drivers/net/wireless/mediatek/mt76/ |
H A D | testmode.c | 1 // SPDX-License-Identifier: ISC 8 [MT76_TM_ATTR_RESET] = { .type = NLA_FLAG }, 9 [MT76_TM_ATTR_STATE] = { .type = NLA_U8 }, 10 [MT76_TM_ATTR_TX_COUNT] = { .type = NLA_U32 }, 11 [MT76_TM_ATTR_TX_LENGTH] = { .type = NLA_U32 }, 12 [MT76_TM_ATTR_TX_RATE_MODE] = { .type = NLA_U8 }, 13 [MT76_TM_ATTR_TX_RATE_NSS] = { .type = NLA_U8 }, 14 [MT76_TM_ATTR_TX_RATE_IDX] = { .type = NLA_U8 }, 15 [MT76_TM_ATTR_TX_RATE_SGI] = { .type = NLA_U8 }, 16 [MT76_TM_ATTR_TX_RATE_LDPC] = { .type = NLA_U8 }, [all …]
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/linux/arch/powerpc/boot/dts/fsl/ |
H A D | t4240qds.dts | 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc. 35 /include/ "t4240si-pre.dtsi" 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "cfi-flash"; 94 bank-width = <2>; 95 device-width = <1>; [all …]
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H A D | t4240rdb.dts | 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc. 35 /include/ "t4240si-pre.dtsi" 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 62 #address-cells = <1>; 63 #size-cells = <1>; 64 compatible = "cfi-flash"; 67 bank-width = <2>; 68 device-width = <1>; [all …]
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H A D | t2080qds.dts | 4 * Copyright 2013 - 2015 Freescale Semiconductor Inc. 35 /include/ "t208xsi-pre.dtsi" 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 66 phy-handle = <&phy_sgmii_s3_1e>; 67 phy-connection-type = "xgmii"; 71 phy-handle = <&phy_sgmii_s3_1f>; 72 phy-connection-type = "xgmii"; 76 phy-handle = <&rgmii_phy1>; [all …]
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H A D | t2081qds.dts | 4 * Copyright 2013 - 2015 Freescale Semiconductor Inc. 35 /include/ "t208xsi-pre.dtsi" 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 58 phy-handle = <&phy_sgmii_s7_1c>; 59 phy-connection-type = "sgmii"; 63 phy-handle = <&phy_sgmii_s7_1d>; 64 phy-connection-type = "sgmii"; 68 phy-handle = <&rgmii_phy1>; [all …]
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H A D | t2080rdb.dts | 2 * T2080PCIe-RDB Board Device Tree Source 4 * Copyright 2014 - 2015 Freescale Semiconductor Inc. 35 /include/ "t208xsi-pre.dtsi" 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 60 phy-handle = <&xg_aq1202_phy3>; 61 phy-connection-type = "xgmii"; 65 phy-handle = <&xg_aq1202_phy4>; 66 phy-connection-type = "xgmii"; [all …]
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H A D | p5040ds.dts | 4 * Copyright 2012 - 2015 Freescale Semiconductor Inc. 35 /include/ "p5040si-pre.dtsi" 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 74 reserved-memory { 75 #address-cells = <2>; 76 #size-cells = <2>; 79 bman_fbpr: bman-fbpr { 83 qman_fqd: qman-fqd { [all …]
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H A D | p4080ds.dts | 4 * Copyright 2009 - 2015 Freescale Semiconductor Inc. 35 /include/ "p4080si-pre.dtsi" 40 #address-cells = <2>; 41 #size-cells = <2>; 42 interrupt-parent = <&mpic>; 62 reserved-memory { 63 #address-cells = <2>; 64 #size-cells = <2>; 67 bman_fbpr: bman-fbpr { 71 qman_fqd: qman-fqd { [all …]
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | phy-cadence-torrent.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Cadence Torrent SD0801 PHY 10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY) 12 PHY also supports multilink multiprotocol combinations including protocols 16 - Swapnil Jakhade <sjakhade@cadence.com> 17 - Yuti Amonkar <yamonkar@cadence.com> 22 - cdns,torrent-phy [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | phy-stm32-usbphyc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 USB HS PHY controller 11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI 12 switch. It controls PHY configuration and status, and the UTMI+ switch that 13 selects either OTG or HOST controller for the second PHY port. It also sets 19 |_ PHY port#1 _________________ HOST controller 22 |_ PHY port#2 ----| |________________ [all …]
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/linux/Documentation/devicetree/bindings/mmc/ |
H A D | marvell,xenon-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 mmc-controller.yaml and the properties used by the Xenon implementation. 15 sets, clock and PHY. 20 - Ulf Hansson <ulf.hansson@linaro.org> 25 - enum: 26 - marvell,armada-cp110-sdhci 27 - marvell,armada-ap806-sdhci [all …]
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/linux/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_phy.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 64 * ixgbe_ones_comp_byte_add - Perform one's complement addition 68 * Returns one's complement 8-bit sum. 79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 91 u32 swfw_mask = hw->phy.phy_semaphore_mask; in ixgbe_read_i2c_combined_generic_int() 104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) in ixgbe_read_i2c_combined_generic_int() 105 return -EBUSY; in ixgbe_read_i2c_combined_generic_int() [all …]
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/linux/Documentation/devicetree/bindings/soc/rockchip/ |
H A D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 15 - items: 16 - enum: 17 - rockchip,rk3288-sgrf 18 - rockchip,rk3566-pipe-grf 19 - rockchip,rk3568-pcie3-phy-grf 20 - rockchip,rk3568-pipe-grf [all …]
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/linux/drivers/net/ethernet/intel/igb/ |
H A D | e1000_82575.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 61 * igb_write_vfta_i350 - Write value to VLAN filter table 71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350() 74 for (i = 10; i--;) in igb_write_vfta_i350() 78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350() 82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575() 114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked 121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap() local [all …]
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/linux/drivers/net/ethernet/intel/e1000e/ |
H A D | ich8lan.c | 1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 5 * 82562G-2 10/100 Network Connection 7 * 82562GT-2 10/100 Network Connection 9 * 82562V-2 10/100 Network Connection 10 * 82566DC-2 Gigabit Network Connection 12 * 82566DM-2 Gigabit Network Connection 19 * 82567LM-2 Gigabit Network Connection 20 * 82567LF-2 Gigabit Network Connection 21 * 82567V-2 Gigabit Network Connection [all …]
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