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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dsamsung,usb3-drd-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
16 compatible PHYs, the second cell in the PHY specifier identifies the
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H A Dqcom,qmp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP PHY controller
11 - Vinod Koul <vkoul@kernel.org>
14 QMP phy controller supports physical layer functionality for a number of
20 - qcom,ipq6018-qmp-pcie-phy
21 - qcom,ipq6018-qmp-usb3-phy
22 - qcom,ipq8074-qmp-gen3-pcie-phy
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H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
29 abstraction of the signals that are routed to a USB receptacle (i.e. a PHY
30 for the USB signal, the VBUS power supply, the USB 2.0 companion port for
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H A Dphy-stm32-usbphyc.txt1 STMicroelectronics STM32 USB HS PHY controller
3 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
4 switch. It controls PHY configuration and status, and the UTMI+ switch that
5 selects either OTG or HOST controller for the second PHY port. It also sets
11 |_ PHY port#1 _________________ HOST controller
14 |_ PHY port#2 ----| |________________
19 Phy provider node
23 - compatible: must be "st,stm32mp1-usbphyc"
24 - reg: address and length of the usb phy control register set
25 - clocks: phandle + clock specifier for the PLL phy clock
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H A Dqcom,qusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm QUSB2 phy controller
11 - Wesley Cheng <quic_wcheng@quicinc.com>
19 - items:
20 - enum:
21 - qcom,ipq6018-qusb2-phy
22 - qcom,ipq8074-qusb2-phy
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H A Dqcom,usb-hs-28nm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
18 - qcom,usb-hs-28nm-femtophy
23 "#phy-cells":
28 - description: rpmcc ref clock
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H A Dqcom,qmp-usb3-dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm QMP USB3 DP PHY controller
11 - Wesley Cheng <quic_wcheng@quicinc.com>
16 - qcom,sc7180-qmp-usb3-dp-phy
17 - qcom,sc7280-qmp-usb3-dp-phy
18 - qcom,sc8180x-qmp-usb3-dp-phy
19 - qcom,sc8280xp-qmp-usb43dp-phy
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H A Dallwinner,sun8i-h3-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H3 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-h3-usb-phy
20 - allwinner,sun50i-h616-usb-phy
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H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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H A Dqcom,usb-snps-femto-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2
10 - Wesley Cheng <quic_wcheng@quicinc.com>
13 Qualcomm High-Speed USB PHY
18 - items:
19 - enum:
20 - qcom,sa8775p-usb-hs-phy
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H A Dqcom,sc7180-qmp-usb3-dp-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,sc7180-qmp-usb3-dp-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm QMP USB3 DP PHY controller (SC7180)
11 The QMP PHY controller supports physical layer functionality for a number of
15 qcom,sc8280xp-qmp-usb43dp-phy.yaml.
18 - Wesley Cheng <quic_wcheng@quicinc.com>
23 - enum:
24 - qcom,sc7180-qmp-usb3-dp-phy
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H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller
11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
12 switch. It controls PHY configuration and status, and the UTMI+ switch that
13 selects either OTG or HOST controller for the second PHY port. It also sets
19 |_ PHY port#1 _________________ HOST controller
22 |_ PHY port#2 ----| |________________
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H A Dallwinner,sun6i-a31-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun6i-a31-usb-phy
22 - description: PHY Control registers
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H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidi
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H A Dqcom,qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
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H A Dallwinner,sun8i-a83t-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-a83t-usb-phy
22 - description: PHY Control registers
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H A Dqcom,usb-ss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
10 - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
13 Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
18 - qcom,usb-ss-28nm-phy
23 "#phy-cells":
28 - description: rpmcc clock
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H A Dqcom,snps-eusb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,snps-eusb
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H A Dallwinner,sun4i-a10-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun4i-a10-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 USB PHY
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun4i-a10-usb-phy
20 - allwinner,sun7i-a20-usb-phy
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H A Dqcom,hdmi-phy-other.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/phy/qcom,hdmi-phy-other.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Qualcomm Adreno/Snapdragon HDMI phy
11 - Rob Clark <robdclark@gmail.com>
16 - qcom,hdmi-phy-8660
17 - qcom,hdmi-phy-8960
18 - qcom,hdmi-phy-8974
19 - qcom,hdmi-phy-8084
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H A Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
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/freebsd/sys/contrib/device-tree/Bindings/ufs/
H A Dufs-qcom.txt1 * Qualcomm Technologies Inc Universal Flash Storage (UFS) PHY
3 UFSPHY nodes are defined to describe on-chip UFS PHY hardware macro.
4 Each UFS PHY node should have its own node.
6 To bind UFS PHY with UFS host controller, the controller node should
7 contain a phandle reference to UFS PHY node.
10 - compatible : compatible list, contains one of the following -
11 "qcom,ufs-phy-qmp-20nm" for 20nm ufs phy,
12 "qcom,ufs-phy-qmp-14nm" for legacy 14nm ufs phy,
13 "qcom,msm8996-ufs-phy-qmp-14nm" for 14nm ufs phy
15 - reg : should contain PHY register address space (mandatory),
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/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3229-xms6.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/input/input.h>
23 dc_12v: dc-12v-regulator {
24 compatible = "regulator-fixed";
25 regulator-name = "dc_12v";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-min-microvolt = <12000000>;
29 regulator-max-microvolt = <12000000>;
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dmsm-hsusb.txt6 - compatible: Should contain "qcom,ehci-host"
7 - regs: offset and length of the register set in the memory map
8 - usb-phy: phandle for the PHY device
13 compatible = "qcom,ehci-host";
15 usb-phy
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/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddsi.txt5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
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