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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dlan9303.txt2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
23 auto-detected and mapped accordingly.
31 fixed-link { /* RMII fixed link to LAN9303 */
33 full-duplex;
38 compatible = "smsc,lan9303-i2c";
[all …]
/linux/drivers/net/ethernet/arc/
H A Demac_mdio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
19 * arc_mdio_complete_wait - Waits until MDIO transaction is completed.
22 * returns: 0 on success, -ETIMEDOUT on a timeout.
34 /* Reset "MDIO complete" flag */ in arc_mdio_complete_wait()
42 return -ETIMEDOUT; in arc_mdio_complete_wait()
46 * arc_mdio_read - MDIO interface read function.
48 * @phy_addr: Address of the PHY device.
49 * @reg_num: PHY register to read.
51 * returns: The register contents on success, -ETIMEDOUT on a timeout.
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk3036-evb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
18 phy = <&phy0>;
19 phy-reset-duration = <10>; /* millisecond */
20 phy-reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; /* PHY_RST */
21 pinctrl-names = "default";
22 pinctrl-0 = <&emac_xfer>, <&emac_mdio>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
H A Drk3036-kylin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
9 compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
18 stdout-path = "serial2:115200n8";
26 hdmi_con: hdmi-con {
27 compatible = "hdmi-connector";
32 remote-endpoint = <&hdmi_out_con>;
37 leds: gpio-leds {
38 compatible = "gpio-leds";
40 work_led: led-0 {
[all …]
/linux/drivers/net/wireless/ath/ath5k/
H A Dreg.h2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
[all …]
H A Dpcu.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
40 * - Buffering of RX and TX frames (after QCU/DCUs)
42 * - Encrypting and decrypting (using the built-in engine)
44 * - Generating ACKs, RTS/CTS frames
46 * - Maintaining TSF
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-duckbill.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2013-2014,2016 Michael Heimpold <mhei@heimpold.de>
4 * Copyright (C) 2015-2017 I2SE GmbH <info@i2se.com>
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
20 reg_3p3v: regulator-3p3v {
21 compatible = "regulator-fixed";
22 regulator-name = "3P3V";
23 regulator-min-microvolt = <3300000>;
24 regulator-max-microvolt = <3300000>;
[all …]
H A Dimx28-duckbill-2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2017 I2SE GmbH <info@i2se.com>
7 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
14 compatible = "i2se,duckbill-2", "fsl,imx28";
21 reg_3p3v: regulator-3p3v {
22 compatible = "regulator-fixed";
23 regulator-name = "3P3V";
24 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx28-cfa10037.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * The CFA-10049 is an expansion board for the CFA-10036 module, thus we
8 * need to include the CFA-10036 DTS.
10 #include "imx28-cfa10036.dts"
13 model = "Crystalfontz CFA-10037 Board";
17 apbh-bus@80000000 {
19 usb_pins_cfa10037: usb-10037@0 {
21 fsl,pinmux-ids = <
24 fsl,drive-strength = <MXS_DRIVE_4mA>;
26 fsl,pull-up = <MXS_PULL_DISABLE>;
[all …]
H A Dimx28-cfa10058.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * The CFA-10058 is an expansion board for the CFA-10036 module, thus we
9 * need to include the CFA-10036 DTS.
11 #include "imx28-cfa10036.dts"
14 model = "Crystalfontz CFA-10058 Board";
17 reg_usb1_vbus: regulator-0 {
18 compatible = "regulator-fixed";
19 pinctrl-names = "default";
20 pinctrl-0 = <&usb_pins_cfa10058>;
21 regulator-name = "usb1_vbus";
[all …]
H A Dimx28-cfa10057.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * The CFA-10057 is an expansion board for the CFA-10036 module, thus we
9 * need to include the CFA-10036 DTS.
11 #include "imx28-cfa10036.dts"
14 model = "Crystalfontz CFA-10057 Board";
17 reg_usb1_vbus: regulator-0 {
18 compatible = "regulator-fixed";
19 pinctrl-names = "default";
20 pinctrl-0 = <&usb_pins_cfa10057>;
21 regulator-name = "usb1_vbus";
[all …]
H A Dimx28-m28cu3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 /dts-v1/;
19 compatible = "pwm-backlight";
21 brightness-levels = <0 4 8 16 32 64 128 255>;
22 default-brightness-level = <6>;
26 compatible = "gpio-leds";
27 pinctrl-names = "default";
28 pinctrl-0 = <&led_pins_gpio>;
31 label = "sd0-led";
33 linux,default-trigger = "mmc0";
[all …]
H A Dimx28-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
10 compatible = "fsl,imx28-evk", "fsl,imx28";
18 reg_3p3v: regulator-3p3v {
19 compatible = "regulator-fixed";
20 regulator-name = "3P3V";
21 regulator-min-microvolt = <3300000>;
22 regulator-max-microvolt = <3300000>;
23 regulator-always-on;
26 reg_vddio_sd0: regulator-vddio-sd0 {
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-imx6ull-opos6ul.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
8 reg = <0x80000000 0>; /* will be filled by U-Boot */
11 reg_3v3: regulator-3v3 {
12 compatible = "regulator-fixed";
13 regulator-name = "3V3";
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
18 usdhc3_pwrseq: usdhc3-pwrseq {
19 compatible = "mmc-pwrseq-simple";
20 reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
[all …]
H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 power-supply = <&reg_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
33 gpio_buttons: gpio-keys {
[all …]
H A Dimx6qdl-apf6.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 reg_1p8v: regulator-1p8v {
10 compatible = "regulator-fixed";
11 regulator-name = "1P8V";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <1800000>;
14 regulator-always-on;
15 vin-supply = <&reg_3p3v>;
[all …]
H A Dimx51-ts4800.dts2 * Copyright 2015 Savoir-faire Linux
4 * This device tree is based on imx51-babbage.dts
9 /dts-v1/;
13 model = "Technologic Systems TS-4800";
14 compatible = "technologic,imx51-ts4800", "fsl,imx51";
17 stdout-path = &uart1;
27 clock-frequency = <22579200>;
31 clock-frequency = <24576000>;
35 backlight_reg: regulator-backlight {
36 compatible = "regulator-fixed";
[all …]
H A Dimx6ul-pico.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
20 stdout-path = &uart6;
24 compatible = "pwm-backlight";
26 brightness-levels = <0 4 8 16 32 64 128 255>;
27 default-brightness-level = <6>;
31 reg_2p5v: regulator-2p5v {
32 compatible = "regulator-fixed";
33 regulator-name = "2P5V";
34 regulator-min-microvolt = <2500000>;
[all …]
H A Dimx6ul-ccimx6ulsbcpro.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
13 #include "imx6ul-ccimx6ulsom.dtsi"
20 compatible = "pwm-backlight";
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <6>;
29 power-supply = <&ldo4_ext>;
34 remote-endpoint = <&display_out>;
[all …]
/linux/drivers/ata/
H A Dlibata-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
6 * Copyright 2003-2004 Jeff Garzik
19 #include "libata-transport.h"
21 /* debounce timing parameters in msecs { interval, duration, timeout } */
30 * sata_scr_valid - test whether SCRs are accessible
43 struct ata_port *ap = link->ap; in sata_scr_valid()
45 return (ap->flags & ATA_FLAG_SATA) && ap->ops->scr_read; in sata_scr_valid()
50 * sata_scr_read - read SCR register of the specified port
56 * guaranteed to succeed if @link is ap->link, the cable type of
[all …]
/linux/drivers/net/usb/
H A Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
52 #define INT_STS_MAC_RTO_ (0x00040000) /* MAC Reset Time Out */
55 #define INT_STS_PHY_INT_ (0x00008000) /* PHY Interrupt */
83 #define HW_CFG_LRST_ (0x00000008) /* Soft Lite Reset */
84 #define HW_CFG_PSEL_ (0x00000004) /* External PHY Select */
86 #define HW_CFG_SRST_ (0x00000001) /* Soft Reset */
106 #define PM_CTL_PHY_RST_ (0x00000010) /* PHY Reset */
128 #define AFC_CFG_BACK_DUR_ (0x000000F0) /* Back Pressure Duration */
[all …]
/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_pll_8960.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
27 * configuration into common-clock-framework.
239 writel(data, pll->mmio + reg); in pll_write()
244 return readl(pll->mmio + reg); in pll_read()
249 return platform_get_drvdata(pll->pdev); in pll_get_phy()
255 struct hdmi_phy *phy = pll_get_phy(pll); in hdmi_pll_enable() local
261 /* Assert PLL S/W reset */ in hdmi_pll_enable()
266 /* Wait for a short time before de-asserting in hdmi_pll_enable()
269 * to assert and de-assert. in hdmi_pll_enable()
[all …]
/linux/drivers/net/phy/
H A Ddp83td510.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for the Texas Instruments DP83TD510 PHY
10 #include <linux/phy.h>
16 /* Bit 7 - mii_interrupt, active high. Clears on read.
40 * 32-bit or 16-bit counters for TX and RX statistics and must be read in
43 * - DP83TD510E_PKT_STAT_1: Contains TX packet count bits [15:0].
44 * - DP83TD510E_PKT_STAT_2: Contains TX packet count bits [31:16].
45 * - DP83TD510E_PKT_STAT_3: Contains TX error packet count.
46 * - DP83TD510E_PKT_STAT_4: Contains RX packet count bits [15:0].
47 * - DP83TD510E_PKT_STAT_5: Contains RX packet count bits [31:16].
[all …]
H A Ddp83640_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define PHYCR2 0x001c /* PHY Control Register 2 */
20 #define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
21 #define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
30 #define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
36 #define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
37 #define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
41 #define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
42 #define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
43 #define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
172 * This value is in terms of 32-bit words.
175 * @ahbphysync: AHB and PHY Synchronous (AhbPhySync)
[all …]

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