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/linux/Documentation/devicetree/bindings/net/
H A Drockchip-dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/rockchip-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Wu <david.wu@rock-chips.com>
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
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/linux/Documentation/devicetree/bindings/soc/rockchip/
H A Dgrf.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip General Register Files (GRF)
10 - Heiko Stuebner <heiko@sntech.de>
15 - items:
16 - enum:
17 - rockchip,rk3288-sgrf
18 - rockchip,rk3528-ioc-grf
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-rk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DOC: dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
5 * Copyright (C) 2014 Chen-Zhi (Roger Chen)
7 * Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
90 struct regmap *grf; member
103 val = rsd->rgmii_10; in rk_set_reg_speed()
105 val = rsd->rgmii_100; in rk_set_reg_speed()
107 val = rsd->rgmii_1000; in rk_set_reg_speed()
112 return -EINVAL; in rk_set_reg_speed()
116 val = rsd->rmii_10; in rk_set_reg_speed()
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-naneng-combphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
214 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel()
216 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel()
224 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write()
225 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write()
226 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write()
228 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write()
233 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready()
236 mask = GENMASK(cfg->pipe_phy_status.bitend, in rockchip_combphy_is_ready()
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/linux/drivers/clk/rockchip/
H A Dclk-rk3576.c1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Elaine Zhang <zhangqing@rock-chips.com>
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
119 .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_BIGCORE_DIV_MASK, \
126 .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_LITCORE_DIV_MASK, \
133 .val = HIWORD_UPDATE(_pclkdbg - 1, RK3576_PCLK_DBG_LITCORE_DIV_MASK, \
142 HIWORD_UPDATE(_div - 1, RK3576_ACLK_CCI_DIV_MASK, \
390 * CRU Clock-Architecture
1322 /* php */
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