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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-d
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H A Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
25 - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
28 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
32 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
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H A Dsynopsys-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ul
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dsamsung,spi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/samsung,spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for Samsung S3C/S5P/Exynos SoC SPI controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 See spi-peripheral-props.yaml for more info.
16 controller-data:
21 samsung,spi-feedback-delay:
23 The sampling phase shift to be applied on the miso line (to account
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H A Dspi-samsung.txt8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
18 - interrupts: The interrupt number to the cpu. The interrupt specifier format
21 - dmas : Two or more DMA channel specifiers following the convention outlined
24 - dma-names: Names for the dma channels. There must be at least one channel
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/freebsd/contrib/ntp/kernel/sys/
H A Dtimex.h21 * Added defines for hybrid phase/frequency-lock loop.
25 * defines for PPS phase-lock loop.
45 * ntp_gettime - NTP user application interface
56 * ntp_adjtime - NTP daemon application interface
76 * phase-lock loop (PLL) model used in the kernel implementation. These
97 #define SHIFT_KG 6 /* phase factor (shift) */
98 #define SHIFT_KF 16 /* PLL frequency factor (shift) */
99 #define SHIFT_KH 2 /* FLL frequency factor (shift) */
100 #define MAXTC 6 /* maximum time constant (shift) */
105 * possible without overflow of a 32-bit word.
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H A Dbsd_audioirig.h43 #define AUIB_INIT(ib) ((ib)->ib_head = (ib)->ib_tail = (ib)->ib_lock = \
44 (ib)->phase = (ib)->shi = (ib)->slo = (ib)->high = \
45 (ib)->level0 = (ib)->level1 = \
46 (ib)->shift[0] = (ib)->shift[1] = (ib)->shift[2] = \
47 (ib)->shift[3] = (ib)->sdata[0] = (ib)->sdata[1] = \
48 (ib)->sdata[2] = (ib)->sdata[3] = (ib)->err = 0)
49 #define AUIB_EMPTY(ib) ((ib)->ib_head == (ib)->ib_tail)
50 #define AUIB_LEN(ib) (AUIB_MOD((ib)->ib_tail - (ib)->ib_head))
51 #define AUIB_LEFT(ib) (AUIB_MOD((ib)->ib_head - (ib)->ib_tail - 1))
85 u_long eacc; /* 10-bit element accumulator */
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/freebsd/sys/contrib/device-tree/Bindings/leds/backlight/
H A Dsky81452-backlight.txt1 SKY81452-backlight bindings
4 - compatible : Must be "skyworks,sky81452-backlight"
7 - name : Name of backlight device. Default is 'lcd-backlight'.
8 - gpios : GPIO to use to EN pin.
10 - led-sources : List of enabled channels from 0 to 5.
12 - skyworks,ignore-pwm : Ignore both PWM input
13 - skyworks,dpwm-mode : Enable DPWM dimming mode, otherwise Analog dimming.
14 - skyworks,phase-shift : Enable phase shift mode
15 - skyworks,short-detection-threshold-volt
17 - skyworks,current-limit-mA
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/freebsd/sys/contrib/openzfs/tests/zfs-tests/cmd/
H A Dxattrtest.c1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
94 static int phase = PHASE_ALL; variable
103 "usage: %s [-hvycdrRk] [-n <nth>] [-f <files>] [-x <xattrs>]\n" in usage()
104 " [-s <bytes>] [-p <path>] [-t <script> ] [-o <phase>]\n", in usage()
108 " --help -h This help\n" in usage()
109 " --verbose -v Increase verbosity\n" in usage()
110 " --verify -y Verify xattr contents\n" in usage()
111 " --nth -n <nth> Print every nth file\n" in usage()
112 " --files -f <files> Set xattrs on N files\n" in usage()
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/freebsd/sys/kern/
H A Dkern_ntptime.c1 /*-
4 * Copyright (c) David L. Mills 1993-2001 *
22 * Poul-Henning Kamp <phk@FreeBSD.org>.
57 * Single-precision macros for 64-bit machines
61 #define L_SUB(v, u) ((v) -= (u))
63 #define L_NEG(v) ((v) = -(v))
67 (v) = -(-(v) >> (n)); \
77 ((v) = -((int64_t)(-(a)) << 32)); \
81 #define L_GINT(v) ((v) < 0 ? -(-(v) >> 32) : (v) >> 32)
93 * phase and frequency of the clock discipline loop which controls the
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/freebsd/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Daarch64.h1 //=== aarch64.h - Generic JITLink aarch64 edge kinds, utilities -*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
24 /// Represents aarch64 fixups and other aarch64-specific edge kinds.
27 /// A plain 64-bit pointer value relocation.
30 /// Fixup <- Target + Addend : uint64
34 /// A plain 32-bit pointer value relocation.
37 /// Fixup <- Target + Addend : uint32
40 /// - The target must reside in the low 32-bits of the address space,
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/freebsd/contrib/ntp/util/
H A Dkern.c2 * This program simulates a first-order, type-II phase-lock loop using
21 * Phase-lock loop definitions
24 #define MAXPHASE 512000 /* max phase error (us) */
26 #define TAU 2 /* time constant (shift 0 - 6) */
45 * Phase-lock loop variables
54 long time_phase = 0; /* phase offset (scaled us) */
90 timey -= 1000000; in main()
93 timex.tv_usec -= 1000000; in main()
98 timez = (long)timey - timex.tv_usec; in main()
100 timez -= 1000000; in main()
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/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/modes/
H A Dgcm_pclmulqdq.S1 // SPDX-License-Identifier: CDDL-1.0
10 * or https://opensource.org/licenses/CDDL-1.0.
33 * Accelerated GHASH implementation with Intel PCLMULQDQ-NI
37 * PCLMULQDQ is used to accelerate the most time-consuming part of GHASH,
38 * carry-less multiplication. More information about PCLMULQDQ can be
40 * http://software.intel.com/en-us/articles/
41 * carry-less-multiplication-and-its-usage-for-computing-the-gcm-mode/
70 * 5. Added code to byte swap 16-byte input and output.
100 * Use this mask to byte-swap a 16-byte integer with the pshufb instruction
114 * Perform a carry-less multiplication (that is, use XOR instead of the
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Daltr_socfpga.txt5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
18 - #clock-cells : from common clock binding, shall be set to 0.
21 - fixed-divider : If clocks have a fixed divider value, use this property.
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dapll.txt4 register-mapped APLL with usually two selectable input clocks
5 (reference clock and bypass clock), with analog phase locked
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
16 - #clock-cells : from common clock binding; shall be set to 0.
17 - clocks : link phandles of parent clocks (clk-ref and clk-bypass)
18 - reg : address and length of the register set for controlling the APLL.
20 "control" - contains the control register offset
21 "idlest" - contains the idlest register offset
22 "autoidle" - contains the autoidle register offset (OMAP2 only)
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/freebsd/contrib/netbsd-tests/fs/ffs/
H A Dffs_common.sh5 local endian=$1; shift
6 local vers=$1; shift
7 local type=$1; shift
10 op="-q user -q group"
12 op="-q ${type}"
14 atf_check -o ignore -e ignore newfs ${op} \
15 -B ${endian} -O ${vers} -s 4000 -F ${IMG}
20 local sarg=$1; shift
22 atf_check -o ignore -e ignore $(atf_get_srcdir)/h_ffs_server \
29 atf_check -s exit:0 env RUMP_SERVER=unix://${s} rump.halt;
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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dnxp,pf8x00-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/nxp,pf8x00-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jagan Teki <jagan@amarulasolutions.com>
11 - Troy Kisky <troy.kisky@boundarydevices.com>
16 linear and one vsnvs regulators. It has built-in one time programmable
22 - nxp,pf8100
23 - nxp,pf8121a
24 - nxp,pf8200
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/freebsd/lib/libsys/
H A Dntp_adjtime.261 to adjust the phase and frequency of the phase- or frequency-lock loop
78 .Bd -literal
91 * The following read-only structure members are implemented
97 int shift; /* interval duration (s) (shift) (ro) */
109 .Bl -tag -width tolerance -compact
113 call (write-only).
115 .Bl -tag -width MOD_TIMECONST -compact -offset indent
135 system time in small increments (read-write).
137 Frequency offset (scaled ppm) (read-write).
143 error bound growth (read-write).
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/freebsd/usr.sbin/ntp/scripts/
H A Dntptrace1 #! /usr/local/bin/perl -w
4 # John Hay -- John.Hay@icomtek.csir.co.za / jhay@FreeBSD.org
17 $host = shift;
22 $cmd = "$ntpq -n -c rv $host";
27 # Very old servers report phase and not offset.
28 $offset = $1 if (/(?:offset|phase)=([^\s,]+)/);
51 $cmd = "$ntpq -n -c \"pstat $peer\" $host";
/freebsd/contrib/llvm-project/libunwind/src/
H A DUnwind-EHABI.cpp1 //===----------------------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 // Implements ARM zero-cost C++ exceptions
10 //===----------------------------------------------------------------------===//
12 #include "Unwind-EHABI.h"
35 return byteData[(offset & ~(size_t)0x03) + (3 - (offset & (size_t)0x03))]; in getByte()
56 SU16 = 0, // Short descriptor, 16-bit entries
57 LU16 = 1, // Long descriptor, 16-bit entries
58 LU32 = 3, // Long descriptor, 32-bit entries
110 // See # 9.2 table for decoding the kind of descriptor. It's a 2-bit value. in ProcessDescriptors()
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/
H A Dgcc_personality_v0.c1 //===-- gcc_personality_v0.c - Implement __gcc_personality_v0 -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 * - libcompiler_rt
16 * - libgcc_eh
17 * - libgcc_s
19 * In the former, the include path points to the contrib/libcxxrt/unwind-arm.h
24 * provided in the "helpful" header below, and libcxxrt's unwind-arm.h provides
33 // order to provide forward compatibility for such compilers, we re-declare the
36 #include "unwind-ehabi-helpers.h"
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dsky81452.txt4 - compatible : Must be "skyworks,sky81452"
5 - reg : I2C slave address
8 - backlight : container node for backlight following the binding
9 in leds/backlight/sky81452-backlight.txt
10 - regulator : container node for regulators following the binding
11 in regulator/sky81452-regulator.txt
20 compatible = "skyworks,sky81452-backlight";
21 name = "pwm-backlight";
22 led-sources = <0 1 2 3 6>;
23 skyworks,ignore-pwm;
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/freebsd/lib/libc/locale/
H A Dmskanji.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
6 * Copyright (c) 2002-2004 Tim J. Robbins. All rights reserved.
10 * (C) Sin'ichiro MIYATANI / Phase One, Inc
28 * This product includes software developed by Phase One, Inc.
29 * 4. The name of Phase One, Inc. may be used to endorse or promote products
75 l->__mbrtowc = _MSKanji_mbrtowc; in _MSKanji_init()
76 l->__wcrtomb = _MSKanji_wcrtomb; in _MSKanji_init()
77 l->__mbsnrtowcs = _MSKanji_mbsnrtowcs; in _MSKanji_init()
78 l->__wcsnrtombs = _MSKanji_wcsnrtombs; in _MSKanji_init()
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/freebsd/crypto/openssl/crypto/modes/asm/
H A Dghashv8-armx.pl2 # Copyright 2014-2025 The OpenSSL Project Authors. All Rights Reserved.
17 # GHASH for ARMv8 Crypto Extension, 64-bit polynomial multiplication.
22 # Biesheuvel of Linaro from bits-n-pieces from other assembly modules.
23 # Just like aesv8-armx.pl this module supports both AArch32 and
28 # Implement 2x aggregated reduction [see ghash-x86.pl for background
34 # improve performance by 20-70% depending on processor.
38 # 64-bit PMULL 32-bit PMULL 32-bit NEON(*)
40 # Cortex-A53 0.85 1.01 8.39
41 # Cortex-A57 0.73 1.17 7.61
52 $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
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/freebsd/crypto/openssl/util/
H A Dmkerr.pl2 # Copyright 1999-2024 The OpenSSL Project Authors. All Rights Reserved.
32 sub phase subroutine
34 my $text = uc(shift);
35 print STDERR "\n---\n$text\n" if $debug;
45 -conf FILE Use the named config file FILE instead of the default.
47 -debug Verbose output debugging on stderr.
49 -internal Generate code that is to be built as part of OpenSSL itself.
52 -module M Only useful with -internal!
55 -rebuild.
59 -nowrite Do not write the header/source files, even if changed.
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