| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | mipi-dsi-bus.txt | 15 The following assumes that only a single peripheral is connected to a DSI
34 conjunction with another DSI host to drive the same peripheral. Hardware
39 DSI peripheral
52 - reg: The virtual channel number of a DSI peripheral. Must be in the range
58 that the peripheral responds to.
59 - If the virtual channels that a peripheral responds to are consecutive, the
79 connected to this peripheral. Each DSI host's output endpoint can be linked to
80 an input endpoint of the DSI peripheral.
87 - (1), (2) and (3) are examples of a DSI host and peripheral on the DSI bus
89 - (4) is an example of a peripheral on a I2C control bus connected to a
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | pistachio-clock.txt | 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
44 Peripheral clock controller:
47 The peripheral clock controller generates clocks for the DDR, ROM, and other
48 peripherals. The peripheral system clock ("periph_sys") generated by the core
49 clock controller is the input clock to the peripheral clock controller.
53 - reg: Must contain the base address and length of the peripheral clock
58 - clock-names: Must include "periph_sys", the peripheral system clock generated
71 Peripheral general control:
74 The peripheral general control block generates system interface clocks and
75 resets for various peripherals. It also contains miscellaneous peripheral
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| H A D | img,pistachio-clk.yaml | 13 Pistachio has four clock controllers (core clock, peripheral clock, peripheral
22 Peripheral clock controller:
24 The peripheral clock controller generates clocks for the DDR, ROM, and other
25 peripherals. The peripheral system clock ("periph_sys") generated by the core
26 clock controller is the input clock to the peripheral clock controller.
28 Peripheral general control:
30 The peripheral general control block generates system interface clocks and
31 resets for various peripherals. It also contains miscellaneous peripheral
98 - description: Peripheral system clock
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| H A D | mvebu-gated-clock.txt | 4 peripheral clocks to be gated to save some power. The clock consumer
11 ID Clock Peripheral
28 ID Clock Peripheral
55 ID Clock Peripheral
82 ID Clock Peripheral
96 ID Clock Peripheral
123 ID Clock Peripheral
133 ID Clock Peripheral
149 22 pdma Peripheral DMA
156 ID Clock Peripheral
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| H A D | marvell-armada-370-gating-clock.yaml | 13 Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some peripheral
20 ID Clock Peripheral
38 ID Clock Peripheral
66 ID Clock Peripheral
94 ID Clock Peripheral
109 ID Clock Peripheral
137 ID Clock Peripheral
148 ID Clock Peripheral
164 22 pdma Peripheral DMA
172 ID Clock Peripheral
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| H A D | st,stm32mp25-rcc.yaml | 107 - description: CK_SCMI_ICN_APB1 Peripheral bridge 1
108 - description: CK_SCMI_ICN_APB2 Peripheral bridge 2
109 - description: CK_SCMI_ICN_APB3 Peripheral bridge 3
110 - description: CK_SCMI_ICN_APB4 Peripheral bridge 4
111 - description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub
112 - description: CK_SCMI_TIMG1 Peripheral bridge for timer1
113 - description: CK_SCMI_TIMG2 Peripheral bridge for timer2
|
| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | mc-peripheral-props.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
10 Many Memory Controllers need to add properties to peripheral devices.
13 to be defined in the peripheral node because they are per-peripheral
38 - $ref: intel,ixp4xx-expansion-peripheral-props.yaml#
39 - $ref: qcom,ebi2-peripheral-props.yaml#
40 - $ref: samsung,exynos4210-srom-peripheral-props.yaml#
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | img,pdc-intc.txt | 27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
35 0-7: Peripheral interrupts
39 flags as follows (only 4 valid for peripheral interrupts):
74 <30 4 /* level */>, /* Peripheral 0 (RTC) */
75 <29 4 /* level */>, /* Peripheral 1 (IR) */
76 <31 4 /* level */>; /* Peripheral 2 (WDT) */
82 * An SoC peripheral that is wired through the PDC.
88 // Interrupt source Peripheral 0
89 interrupts = <0 /* Peripheral 0 (RTC) */
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-peripheral-props.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
7 title: Peripheral-specific properties for a SPI bus.
10 Many SPI controllers need to add properties to peripheral devices. They could
13 properties need to be defined in the peripheral node because they are
14 per-peripheral and there can be multiple peripherals attached to a
125 - $ref: arm,pl022-peripheral-props.yaml#
126 - $ref: cdns,qspi-nor-peripheral-props.yaml#
127 - $ref: fsl,dspi-peripheral-props.yaml#
128 - $ref: samsung,spi-peripheral-props.yaml#
129 - $ref: nvidia,tegra210-quad-peripheral-props.yaml#
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| /freebsd/share/man/man4/ |
| H A D | ppbus.4 | 86 parallel port bus, then initialize it and upper peripheral device drivers.
126 printer or peripheral.
142 adapter and the peripheral.
175 peripheral vendors may implement protocol handshake with the following
178 with your peripheral, allowing the peripheral to request more data, stop the
181 At any time, the peripheral may interrupt the host with the nAck signal without
191 Bidirectional Parallel Peripheral Interface for Personal Computers".
196 also specifies a format for a peripheral identification string and a method of
207 The computer acts as master and the peripheral as slave.
215 it is supported by the peripheral, then to enter one of the forward idle
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| /freebsd/sys/arm64/coresight/ |
| H A D | coresight_funnel.h | 51 #define FUNNEL_PERIPH4 0xFD0 /* Peripheral ID4 */
52 #define FUNNEL_PERIPH5 0xFD4 /* Peripheral ID5 */
53 #define FUNNEL_PERIPH6 0xFD8 /* Peripheral ID6 */
54 #define FUNNEL_PERIPH7 0xFDC /* Peripheral ID7 */
55 #define FUNNEL_PERIPH0 0xFE0 /* Peripheral ID0 */
56 #define FUNNEL_PERIPH1 0xFE4 /* Peripheral ID1 */
57 #define FUNNEL_PERIPH2 0xFE8 /* Peripheral ID2 */
58 #define FUNNEL_PERIPH3 0xFEC /* Peripheral ID3 */
|
| H A D | coresight_tmc.h | 104 #define TMC_PERIPHID4 0xFD0 /* Peripheral ID4 Register */
105 #define TMC_PERIPHID5 0xFD4 /* Peripheral ID5 Register */
106 #define TMC_PERIPHID6 0xFD8 /* Peripheral ID6 Register */
107 #define TMC_PERIPHID7 0xFDC /* Peripheral ID7 Register */
108 #define TMC_PERIPHID0 0xFE0 /* Peripheral ID0 Register */
109 #define TMC_PERIPHID1 0xFE4 /* Peripheral ID1 Register */
110 #define TMC_PERIPHID2 0xFE8 /* Peripheral ID2 Register */
111 #define TMC_PERIPHID3 0xFEC /* Peripheral ID3 Register */
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| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | samsung,sysmmu.yaml | 14 physical memory chunks visible as a contiguous region to DMA-capable peripheral
23 System MMUs are in many to one relation with peripheral devices, i.e. single
24 peripheral device might have multiple System MMUs (usually one for each bus
25 master), but one System MMU can handle transactions from only one peripheral
26 device. The relation between a System MMU and the peripheral device needs to be
27 defined in device node of the peripheral device.
37 For information on assigning System MMU controller to its peripheral devices,
|
| /freebsd/sys/contrib/device-tree/Bindings/display/panel/ |
| H A D | sharp,lq101r1sx01.txt | 7 Each of the DSI channels controls a separate DSI peripheral. The peripheral
9 peripheral and controls the device. The 'link2' property contains a phandle
10 to the peripheral driven by the second link (DSI-LINK2, right or odd).
20 - reg: DSI virtual channel of the peripheral
23 - link2: phandle to the DSI peripheral on the secondary link. Note that the
|
| H A D | sharp,lq101r1sx01.yaml | 17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
19 peripheral and controls the device. The 'link2' property contains a phandle
20 to the peripheral driven by the second link (DSI-LINK2, right or odd).
49 phandle to the DSI peripheral on the secondary link. Note that the
|
| H A D | jdi,lpm102a188a.yaml | 17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1) is considered the primary peripheral
20 peripheral driven by the second link (DSI-LINK2).
43 phandle to the DSI peripheral on the secondary link. Note that the
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | atmel-usb.txt | 10 - clocks: Should reference the peripheral, host and system clocks
12 "ohci_clk" for the peripheral clock
37 - clocks: Should reference the peripheral and the UTMI clocks
39 "ehci_clk" for the peripheral clock
64 - clocks: Should reference the peripheral and the AHB clocks
66 "pclk" for the peripheral clock
95 - clocks: Should reference the peripheral and host clocks
97 "pclk" for the peripheral clock
|
| /freebsd/sys/contrib/dev/iwlwifi/pcie/ |
| H A D | iwl-context-info-v2.h | 223 * struct iwl_prph_scratch - peripheral scratch mapping
239 * struct iwl_prph_info - peripheral information
242 * @sleep_notif: indicates the peripheral sleep status
256 * @config: context in which the peripheral would execute - a subset of
257 * capability csr register published by the peripheral
258 * @prph_info_base_addr: the peripheral information structure start address
277 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after
279 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after
290 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral
291 * after updating the Peripheral Information structure
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| /freebsd/sys/contrib/edk2/Include/Pi/ |
| H A D | PiStatusCode.h | 359 /// Peripheral Subclass definitions.
382 /// Peripheral Class Progress Code definitions.
397 // Peripheral Class Unspecified Subclass Progress Code definitions.
401 /// Peripheral Class Keyboard Subclass Progress Code definitions.
409 /// Peripheral Class Mouse Subclass Progress Code definitions.
416 // Peripheral Class Local Console Subclass Progress Code definitions.
420 // Peripheral Class Remote Console Subclass Progress Code definitions.
424 /// Peripheral Class Serial Port Subclass Progress Code definitions.
431 // Peripheral Class Parallel Port Subclass Progress Code definitions.
435 // Peripheral Class Fixed Media Subclass Progress Code definitions.
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | hisilicon,hix5hd2-sata-phy.yaml | 22 hisilicon,peripheral-syscon:
23 description: Phandle of syscon used to control peripheral
27 … description: Offset and bit number within peripheral-syscon register controlling SATA power supply
30 - description: Offset within peripheral-syscon register
46 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
|
| H A D | phy-hi3798cv200-combphy.txt | 6 registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
21 peripheral controller, as a 3 integers tuple:
27 - The device node should be a child of peripheral controller that contains
29 Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
34 perictrl: peripheral-controller@8a20000 {
|
| H A D | hix5hd2-phy.txt | 11 - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
12 - hisilicon,power-reg: offset and bit number within peripheral-syscon,
20 hisilicon,peripheral-syscon = <&peripheral_ctrl>;
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | atmel,at91rm9200-pinctrl.yaml | 52 Each column will represent the possible peripheral of the pinctrl
58 Peripheral: 2 ( A and B)
66 For each peripheral/bank we will describe in a u32 if a pin can be
69 Let's take the pioA on peripheral B whose value is 0xffc00c3b
71 Peripheral B
142 Peripheral function
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | qcom,spmi-pmic.txt | 56 Required properties for peripheral child nodes:
57 - compatible: Should contain "qcom,xxx", where "xxx" is a peripheral name.
59 Optional properties for peripheral child nodes:
66 example below the rtc device node represents a peripheral of pm8941
67 SID = 0. The regulator device node represents a peripheral of pm8941 SID = 1.
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| /freebsd/sys/contrib/device-tree/Bindings/net/can/ |
| H A D | st,stm32-bxcan.yaml | 24 Primary mode of the bxCAN peripheral is only relevant if the chip has
27 Not to be used if the peripheral is in single CAN configuration.
34 Secondary mode of the bxCAN peripheral is only relevant if the chip
37 Not to be used if the peripheral is in single CAN configuration.
70 secondary) in dual CAN peripheral configuration.
|