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/linux/Documentation/devicetree/bindings/dvfs/
H A Dperformance-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic performance domains
10 - Sudeep Holla <sudeep.holla@arm.com>
13 This binding is intended for performance management of groups of devices or
14 CPUs that run in the same performance domain. Performance domains must not
15 be confused with power domains. A performance domain is defined by a set
16 of devices that always have to run at the same performance level. For a given
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/linux/Documentation/arch/powerpc/
H A Dassociativity.rst6 domains of substantially similar mean performance relative to resources outside
8 performance relative to each other than relative to other resources subsets
9 are represented as being members of a sub-grouping domain. This performance
11 From the platform view, these groups are also referred to as domains.
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
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/linux/Documentation/netlink/specs/
H A Ddev-energymodel.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 ---
6 name: dev-energymodel
13 uapi-header: linux/dev_energymodel.h
16 -
18 name: perf-state-flags
20 -
21 name: perf-state-inefficient
22 doc: >-
23 The performance state is inefficient. There is in this perf-domain,
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/linux/arch/arm64/boot/dts/apple/
H A Dt600x-common.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
11 #address-cells = <2>;
12 #size-cells = <2>;
19 #address-cells = <2>;
20 #size-cells = <0>;
22 cpu-map {
67 enable-method = "spin-table";
68 cpu-release-addr = <0 0>; /* To be filled by loader */
69 next-level-cache = <&l2_cache_0>;
70 i-cache-size = <0x20000>;
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/linux/Documentation/devicetree/bindings/power/
H A Dpower-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic PM domains
10 - Rafael J. Wysocki <rafael@kernel.org>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
15 System on chip designs are often divided into multiple PM domains that can be
17 leakage current. Moreover, in some cases the similar PM domains may also be
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/linux/drivers/pmdomain/arm/
H A Dscmi_perf_domain.c1 // SPDX-License-Identifier: GPL-2.0
3 * SCMI performance domain support.
32 if (!pd->info->set_perf) in scmi_pd_set_perf_state()
36 return -EINVAL; in scmi_pd_set_perf_state()
38 ret = pd->perf_ops->level_set(pd->ph, pd->domain_id, state, false); in scmi_pd_set_perf_state()
40 dev_warn(&genpd->dev, "Failed with %d when trying to set %d perf level", in scmi_pd_set_perf_state()
54 * the performance level can be changed. in scmi_pd_attach_dev()
56 if (!pd->info->set_perf) in scmi_pd_attach_dev()
59 ret = pd->perf_ops->device_opps_add(pd->ph, dev, pd->domain_id); in scmi_pd_attach_dev()
71 if (!pd->info->set_perf) in scmi_pd_detach_dev()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "SCMI performance domain driver"
8 This enables support for the SCMI performance domains which can be
20 This enables support for the SCMI power domains which can be
33 This enables support for the SCPI power domains which can be
/linux/drivers/base/power/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/power/common.c - Common device power management code.
19 * dev_pm_get_subsys_data - Create or refcount power.subsys_data for device.
32 return -ENOMEM; in dev_pm_get_subsys_data()
34 spin_lock_irq(&dev->power.lock); in dev_pm_get_subsys_data()
36 if (dev->power.subsys_data) { in dev_pm_get_subsys_data()
37 dev->power.subsys_data->refcount++; in dev_pm_get_subsys_data()
39 spin_lock_init(&psd->lock); in dev_pm_get_subsys_data()
40 psd->refcount = 1; in dev_pm_get_subsys_data()
41 dev->power.subsys_data = psd; in dev_pm_get_subsys_data()
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/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek-hw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Yuan <hector.yuan@mediatek.com>
19 const: mediatek,cpufreq-hw
29 "#performance-domain-cells":
31 Number of cells in a performance domain specifier.
33 performance domains.
37 - compatible
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/linux/Documentation/admin-guide/pm/
H A Dintel_uncore_frequency_scaling.rst1 .. SPDX-License-Identifier: GPL-2.0
8 :Copyright: |copy| 2022-2023 Intel Corporation
13 ------------
17 performance, SoCs have internal algorithms for scaling uncore frequency. These
20 It is possible that users have different expectations of uncore performance and
22 the scaling min/max frequencies via cpufreq sysfs to improve CPU performance.
25 different core and uncore performance at distinct phases and they may want to
27 improve overall performance.
30 ---------------
45 This is a read-only attribute. If users adjust max_freq_khz,
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/linux/Documentation/driver-api/cxl/platform/acpi/
H A Dsrat.rst1 .. SPDX-License-Identifier: GPL-2.0
4 SRAT - Static Resource Affinity Table
8 affinity to "Proximity Domains". This table is technically optional, but for
9 performance information (see "HMAT") to be enumerated by linux it must be
13 created. If things don't look quite the way you expect - check the SRAT Memory
18 proximity domains. See linux numa creation for more information about how
23 A proximity domain is ROUGHLY equivalent to "NUMA Node" - though a 1-to-1
30 programming in BIOS - an SRAT entry for that memory needs to be present.
36 Proximity Domain : 00000001 <- NUMA Node 1
38 Base Address : 000000C050000000 <- Physical Memory Region
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/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,sm8350-videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8350-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,videocc-sm8350.h
18 include/dt-bindings/reset/qcom,videocc-sm8350.h
23 - qcom,sc8280xp-videocc
24 - qcom,sm8350-videocc
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H A Dqcom,sc8180x-camcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sc8180x-camcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Satya Priya Kakitapalli <quic_skakitap@quicinc.com>
14 power domains on SC8180X.
16 See also: include/dt-bindings/clock/qcom,sc8180x-camcc.h
20 const: qcom,sc8180x-camcc
24 - description: Camera AHB clock from GCC
25 - description: Board XO source
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H A Dqcom,qcm2290-gpucc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,qcm2290-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,qcm2290-gpucc.h
21 const: qcom,qcm2290-gpucc
28 - description: AHB interface clock,
29 - description: SoC CXO clock
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H A Dqcom,dispcc-sm8x50.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Marek <jonathan@marek.ca>
14 domains on SM8150/SM8250/SM8350.
17 include/dt-bindings/clock/qcom,dispcc-sm8150.h
18 include/dt-bindings/clock/qcom,dispcc-sm8250.h
19 include/dt-bindings/clock/qcom,dispcc-sm8350.h
24 - qcom,sc8180x-dispcc
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H A Dqcom,videocc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Taniya Das <quic_tdas@quicinc.com>
14 domains on Qualcomm SoCs.
17 include/dt-bindings/clock/qcom,sm6350-videocc.h
18 include/dt-bindings/clock/qcom,videocc-sc7180.h
19 include/dt-bindings/clock/qcom,videocc-sc7280.h
20 include/dt-bindings/clock/qcom,videocc-sdm845.h
21 include/dt-bindings/clock/qcom,videocc-sm8150.h
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/linux/Documentation/devicetree/bindings/media/
H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
35 - description: The AHB clock
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/linux/Documentation/power/
H A Dopp.rst2 Operating Performance Points (OPP) Library
5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
19 1.1 What is an Operating Performance Point (OPP)?
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
26 domains to run at lower voltage and frequency while other domains run at
30 the device will support per domain are called Operating Performance Points or
41 - {300000000, 1000000}
42 - {800000000, 1200000}
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/linux/kernel/power/
H A Denergy_model.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2018-2021, Arm ltd.
23 * Mutex serializing the registrations of performance domains and letting
29 * Manage performance domains with IDs. One can iterate the performance domains
46 return (dev->bus == &cpu_subsys); in _is_cpu_device()
60 struct em_dbg_info *em_dbg = s->private; \
65 table = em_perf_state_from_pd(em_dbg->pd); \
66 val = table[em_dbg->ps_id].name; \
77 DEFINE_EM_DBG_SHOW(performance, performance);
99 /* Create per-ps directory */ in em_debug_create_ps()
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/linux/Documentation/devicetree/bindings/interconnect/
H A Dqcom,msm8996.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM8996 Network-On-Chip interconnect
10 - Konrad Dybcio <konradybcio@kernel.org>
19 - qcom,msm8996-a0noc
20 - qcom,msm8996-a1noc
21 - qcom,msm8996-a2noc
22 - qcom,msm8996-bimc
23 - qcom,msm8996-cnoc
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/linux/arch/x86/xen/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
33 bool "Limit Xen pv-domain memory to 512GB"
37 Limit paravirtualized user domains to 512GB of RAM.
40 pv-domains with more than 512 GB of RAM. This option controls the
73 Enabling this option may incur a significant performance overhead.
/linux/drivers/pmdomain/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/base/power/domain.c - Common code related to device power domains.
47 __routine = genpd->dev_ops.callback; \
66 mutex_lock(&genpd->mlock); in genpd_lock_mtx()
72 mutex_lock_nested(&genpd->mlock, depth); in genpd_lock_nested_mtx()
77 return mutex_lock_interruptible(&genpd->mlock); in genpd_lock_interruptible_mtx()
82 return mutex_unlock(&genpd->mlock); in genpd_unlock_mtx()
93 __acquires(&genpd->slock) in genpd_lock_spin()
97 spin_lock_irqsave(&genpd->slock, flags); in genpd_lock_spin()
98 genpd->lock_flags = flags; in genpd_lock_spin()
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/linux/drivers/cpufreq/
H A Dscmi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2021 ARM Ltd.
11 #include <linux/clk-provider.h>
50 priv = policy->driver_data; in scmi_cpufreq_get_rate()
52 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate()
59 * perf_ops->freq_set is not a synchronous, the actual OPP change will
66 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target()
67 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target()
69 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target()
75 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch()
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/linux/Documentation/devicetree/bindings/regulator/
H A Dfixed-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
20 - $ref: regulator.yaml#
21 - if:
25 const: regulator-fixed-clock
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/linux/drivers/opp/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 is called Operating Performance Point or OPP. The actual definitions
11 representing individual voltage domains and provides SOC

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