| /linux/Documentation/driver-api/soundwire/ |
| H A D | bra.rst | 6 -----------
12 ------------
14 The SoundWire 1.x specification provides a mechanism to speed-up
20 one byte per frame with write/read commands. With a typical 48kHz
28 10-byte overhead per frame (header and footer response).
35 (3) The targeted Peripheral device SHALL support the optional Data
36 Port 0, and likewise the Manager SHALL expose audio-like Ports
41 bandwidth. If there are no on-going audio transfers, the entire
48 (5) The number of bits transferred per frame SHALL be a multiple of
61 need to be spaced in time or flow-controlled.
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| /linux/Documentation/devicetree/bindings/serial/ |
| H A D | fsl-imx-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
19 - fsl,imx25-uart
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| /linux/drivers/spi/ |
| H A D | spi-geni-qcom.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
16 #include <linux/soc/qcom/geni-se.h>
109 struct geni_se *se = &mas->se; in spi_slv_setup()
111 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); in spi_slv_setup()
112 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); in spi_slv_setup()
113 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); in spi_slv_setup()
114 dev_dbg(mas->dev, "spi slave setup done\n"); in spi_slv_setup()
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | img,pdc-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/img,pdc-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - James Hogan <jhogan@kernel.org>
19 const: img,pdc-intc
24 interrupt-controller: true
26 '#interrupt-cells':
28 <1st-cell>: The interrupt-number that identifies the interrupt source.
29 0-7: Peripheral interrupts
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| H A D | brcm,bcm6345-l1-intc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm6345-l1-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6345-style Level 1 interrupt controller
10 - Simon Arlott <simon@octiron.net>
18 - 32, 64 or 128 incoming level IRQ lines
20 - Most onchip peripherals are wired directly to an L1 input
22 - A separate instance of the register set for each CPU, allowing individual
23 peripheral IRQs to be routed to any CPU
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| /linux/Documentation/driver-api/ |
| H A D | sm501.rst | 15 ----
27 peripheral set as platform devices for the specific drivers.
29 The core re-uses the platform device system as the platform device
31 need to create a new bus-type and the associated code to go with it.
35 ---------
37 Each peripheral has a view of the device which is implicitly narrowed to
38 the specific set of resources that peripheral requires in order to
43 as this is by-far the most resource-sensitive of the on-chip functions.
59 -------------
66 The PCI driver assumes that the PCI card behaves as per the Silicon
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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|
| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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|
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| /linux/Documentation/driver-api/dmaengine/ |
| H A D | client.rst | 8 ``Documentation/crypto/async-tx-api.rst``
11 Below is a guide to device driver writers on how to use the Slave-DMA API of the
19 - Allocate a DMA slave channel
21 - Set slave and controller specific parameters
23 - Get a descriptor for transaction
25 - Submit the transaction
27 - Issue pending requests and wait for callback notification
40 .. code-block:: c
57 for the peripheral.
66 .. code-block:: c
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| /linux/Documentation/devicetree/bindings/dma/ |
| H A D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
6 - interrupts: Must contain all the per-channel DMA interrupts.
7 - clocks: Must contain an entry for each entry in clock-names.
8 See ../clock/clock-bindings.txt for details.
9 - clock-names: Must include the following entries:
10 - sys: MDC system interface clock.
11 - img,cr-periph: Must contain a phandle to the peripheral control syscon
13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
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| H A D | marvell,mmp-dma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,mmp-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Duje Mihanović <duje.mihanovic@skole.hr>
13 Marvell MMP SoCs may have two types of DMA controllers, peripheral and audio.
18 - marvell,pdma-1.0
19 - marvell,adma-1.0
20 - marvell,pxa910-squ
27 Interrupt lines for the controller, may be shared or one per DMA channel
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| /linux/include/linux/platform_data/ |
| H A D | dma-dw.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2010-2011 ST Microelectronics
22 * struct dw_dma_slave - Controller-specific information about a slave
28 * @p_master: peripheral master for transfers on allocated channel
43 * struct dw_dma_platform_data - Controller configuration parameters
49 * @data_width: Maximum data width supported by hardware per AHB master
51 * @multi_block: Multi block transfers supported by hardware per channel.
53 * per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
54 * @protctl: Protection control signals setting per channel.
|
| /linux/drivers/dma/dw/ |
| H A D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2005-2007 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
14 #include <linux/io-64-nonatomic-hi-lo.h>
33 * Redefine this macro to handle differences between 32- and 64-bit
64 /* per-channel registers */
89 /* iDMA 32-bit support */
96 /* per-channel configuration registers */
101 /* top-level parameters */
108 /* iDMA 32-bit support */
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| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | econet,en751221-timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/econet,en751221-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Caleb James DeLisle <cjd@cjdns.fr>
13 The EcoNet High Precision Timer (HPT) is a timer peripheral found in various
14 EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE
15 count/compare registers and a per-CPU control register, with a single interrupt
16 line using a percpu-devid interrupt mechanism.
21 - const: econet,en751221-timer
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|
| /linux/drivers/extcon/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
11 host USB ports. Many of 30-pin connectors including PDMI are
25 tristate "X-Power AXP288 EXTCON support"
29 Say Y here to enable support for USB peripheral detection
30 and USB MUX switching by X-Power AXP288 PMIC.
49 extcon supports single state per extcon instance.
105 enable a system with an integrated USB OTG dual-role transceiver to
106 function as an USB OTG dual-role device.
154 Say Y here to enable support for USB peripheral and USB host
164 Say Y here to enable support for USB peripheral and USB host
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| /linux/Documentation/devicetree/bindings/spi/ |
| H A D | fsl-imx-cspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - const: fsl,imx1-cspi
19 - const: fsl,imx21-cspi
20 - const: fsl,imx27-cspi
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| /linux/drivers/hid/intel-ish-hid/ipc/ |
| H A D | hw-ish-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (c) 2012-2016, Intel Corporation.
15 /* Peripheral Interrupt Status Register */
17 /* Peripheral Interrupt Mask Register */
20 /*Peripheral Interrupt Status Register */
22 /*Peripheral Interrupt Mask Register */
45 /*** register bits - HISR ***/
130 #define IPC_RMP2_DMA_ENABLED 0x1 /* Value to enable DMA, per D3 RCR */
188 /* todo - temp until PIMR HW ready */
|
| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | renesas,idt821034.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 The time-slots used by the codec must be set and so, the properties
17 'dai-tdm-slot-num', 'dai-tdm-slot-width', 'dai-tdm-slot-tx-mask' and
18 'dai-tdm-slot-rx-mask' must be present in the ALSA sound card node for
19 sub-nodes that involve the codec. The codec uses one 8bit time-slot per
21 'dai-tdm-tdm-slot-with' must be set to 8.
23 The IDT821034 codec also supports 5 gpios (SLIC signals) per channel.
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|
| /linux/Documentation/w1/masters/ |
| H A D | w1-uart.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 …g a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/using-a-u…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
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|
| /linux/drivers/usb/host/ |
| H A D | sl811.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
12 * mode one set of registers is used; in peripheral/slave mode, another.
13 * - SL11H only has some "A" transfer registers from 0x00-0x04
14 * - SL811HS also has "B" registers from 0x08-0x0c
15 * - SL811S (or HS in slave mode) has four A+B sets, at 00, 10, 20, 30
28 /* TRANSFER REGISTERS: host and peripheral sides are similar
65 /* CONTROL REGISTERS: host and peripheral are very different.
85 /* 0x08-0x0c are for the B buffer (not in SL11) */
106 * Only ISO can use more than 64 bytes per packet.
116 /*-------------------------------------------------------------------------*/
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| /linux/arch/powerpc/platforms/512x/ |
| H A D | clock-commonclk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
350 cpmf = get_bit_field(&clkregs->spmr, 16, 4); in get_cpmf_mult_x2()
389 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr"); in get_freq_from_dt()
404 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | dwc2.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
21 - const: ingenic,jz4775-otg
22 - const: ingenic,jz4780-otg
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|
| /linux/include/linux/iio/adc/ |
| H A D | qcom-adc5-gen3-common.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
16 #include <linux/iio/adc/qcom-vadc-common.h>
91 /* 100k pull-up channels */
121 * struct adc5_sdam_data - data per SDAM allocated for adc usage
122 * @base_addr: base address for the ADC SDAM peripheral.
133 * struct adc5_device_data - Top-level ADC device data
134 * @regmap: ADC peripheral register map field.
145 * struct adc5_channel_common_prop - ADC channel properties (common to ADC and TM).
172 * struct tm5_aux_dev_wrapper - wrapper structure around TM auxiliary device
174 * @dev_data: Top-level ADC device data.
|
| /linux/Documentation/devicetree/bindings/arm/firmware/ |
| H A D | linaro,optee-tz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/firmware/linaro,optee-tz.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OP-TEE
10 - Jens Wiklander <jens.wiklander@linaro.org>
13 OP-TEE is a piece of software using hardware features to provide a Trusted
25 const: linaro,optee-tz
31 software is expected to be either a per-cpu interrupt or an
32 edge-triggered peripheral interrupt.
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|