| /freebsd/sys/contrib/device-tree/Bindings/cpufreq/ |
| H A D | apple,cluster-cpufreq.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC cluster cpufreq device
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
14 the cluster management register block. This binding uses the standard
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
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| H A D | cpufreq-qcom-hw.txt | 8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
32 "freq-domain0", "freq-domain1".
34 - #freq-domain-cells:
38 * Property qcom,freq-domain
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| H A D | cpufreq-qcom-hw.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
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| /freebsd/sys/contrib/device-tree/Bindings/cpu/ |
| H A D | cpu-topology.txt | 2 CPU topology binding description
6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
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| /freebsd/sys/contrib/device-tree/Bindings/arm/marvell/ |
| H A D | ap80x-system-controller.txt | 6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
32 * "marvell,ap806-clock"
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| /freebsd/sys/contrib/device-tree/Bindings/opp/ |
| H A D | opp.txt | 2 ----------------------------------------------------
4 Devices work at voltage-current-frequency combinations and some implementations
8 uses CPU as a device.
11 should be used per device.
13 Binding 1: operating-points
16 This binding only supports voltage-frequency pairs.
19 - operating-points: An array of 2-tuples items, and each item consists
20 of frequency and voltage like <freq-kHz vol-uV>.
26 cpu@0 {
27 compatible = "arm,cortex-a9";
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| H A D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | cci.txt | 5 ARM multi-cluster systems maintain intra-cluster coherency through a
11 space and multiple sets of interface control registers, one per slave
21 root node (ie from CPUs perspective as per DT standard).
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
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| H A D | arm,cci-400.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
19 space and multiple sets of interface control registers, one per slave
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
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| H A D | psci.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
15 processors") can be used by Linux to initiate various CPU-centri
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| /freebsd/share/man/man9/ |
| H A D | mbuf.9 | 172 consists of a variable-sized header and a small internal
182 .Bl -tag -width "m_nextpkt" -offset indent
214 .Bd -literal
218 #define M_RDONLY 0x00000008 /* associated data marked read-only */
219 #define M_BCAST 0x00000010 /* send/received as link-level broadcast */
220 #define M_MCAST 0x00000020 /* send/received as link-level multicast */
224 #define M_NOFREE 0x00000200 /* do not free mbuf, embedded in cluster */
226 #define M_TSTMP_HPREC 0x00000800 /* rcv_tstmp is high-prec, typically
227 hw-stamped on port (useful for IEEE 1588
230 #define M_PROTO1 0x00001000 /* protocol-specific */
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| /freebsd/sys/contrib/device-tree/Bindings/remoteproc/ |
| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5
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| H A D | xlnx,zynqmp-r5fss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | apple,aic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
23 - Software triggering (ORed with hw line)
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_nb_regs.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
66 /* [0xc] Force init reset per DECEI mode. */
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
310 /* [0x20] Specifies the state of the CPU with reference to power modes. */
452 Connect to Processor Cluster SYSBARDISABLE. */
455 Connect to Processor Cluster BROADCASTINNER. */
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| /freebsd/sys/sys/ |
| H A D | param.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
52 * documentation/content/en/books/porters-handbook/versions/_index.adoc
56 * X.0-CURRENT before releng/X.0 is created, otherwise 'R' is
62 * kernel's KBI in -CURRENT, one that changes some detail about the system that
66 * to one per day / a couple per week except for security fixes.
84 * kernel-specific routines, and in fact it's fine to do this in code that
118 * Machine-independent constants (some used in following include files).
131 #define NOFILE OPEN_MAX /* max open files per process */
192 #define MCLBYTES (1 << MCLSHIFT) /* size of an mbuf cluster */
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| H A D | buf.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
92 * V - Protected by owning bufobj lock
93 * Q - Protected by the buf queue lock
94 * D - Protected by an dependency implementation specific lock
108 uint64_t b_ckhash; /* B_CKHASH requested check-hash */
115 uint16_t b_subqueue; /* (Q) per-cpu q if any */
150 #define BUF_TRACKING_ENTRY(x) ((x) & (BUF_TRACKING_SIZE - 1))
159 #define b_object b_bufobj->bo_object
215 #define B_NEEDCOMMIT 0x00000002 /* Append-write in progress. */
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| /freebsd/sys/contrib/device-tree/src/arm64/tesla/ |
| H A D | fsd.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
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| /freebsd/sys/arm64/qoriq/ |
| H A D | qoriq_therm.c | 1 /*-
3 * SPDX-License-Identifier: BSD-2-Clause
109 { 0, "cpu", 0 },
116 { 0, "cpu-thermal", 0 },
121 { 0, "ddr-controller", 0 },
122 { 1, "core-cluster", 1 },
127 { 0, "ddr-controller", 0 },
130 { 3, "core-cluster", 3 },
135 { 0, "ddr-controller", 0 },
138 { 3, "core-cluster", 3 },
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| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | fsl-ls1088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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| H A D | fsl-ls1028a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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| /freebsd/share/man/man7/ |
| H A D | tuning.7 | 31 .Sh SYSTEM SETUP - DISKLABEL, NEWFS, TUNEFS, SWAP
63 partitions are read-mostly, with very little writing, while
68 heavily write-loaded partitions will not bleed over into the mostly-read
81 .Dq Li "tunefs -n enable /filesystem" .
82 Softupdates drastically improves meta-data performance, mainly file
103 A number of run-time
117 file systems normally update the last-accessed time of a file or
138 atime turned on for mostly read-only partitions such as
161 or essentially read-only partitions such as
170 File systems tend to store meta-data on power-of-2 boundaries
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| /freebsd/sys/x86/x86/ |
| H A D | local_apic.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
15 * 3. Neither the name of the author nor the names of any co-contributors
98 * I/O interrupts use non-negative IRQ values. These values are used
99 * to mark unused IDT entries or IDT entries reserved for a non-I/O
102 #define IRQ_FREE -1
103 #define IRQ_TIMER -2
104 #define IRQ_SYSCALL -3
105 #define IRQ_DTRACE_RET -4
106 #define IRQ_EVTCHN -5
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| /freebsd/sys/net/ |
| H A D | iflib.c | 1 /*-
2 * Copyright (c) 2014-2018, Matthew Macy <mmacy@mattmacy.io>
107 * - Prefetching in tx cleaning should perhaps be a tunable. The distance ahead
110 * - NFLX's m_free path is dominated by vm-based M_EXT manipulation which
112 * - small packet forwarding which is just returning a single mbuf to
119 * - private structures
120 * - iflib private utility functions
121 * - ifnet functions
122 * - vlan registry and other exported functions
123 * - iflib public core functions
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| /freebsd/sys/kern/ |
| H A D | kern_mbuf.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
65 "Cluster must be smaller than a jumbo page");
71 * Mbuf Clusters (2K, contiguous) are allocated from the Cluster
82 * Thus common-case allocations and locking are simplified:
86 * | .------------>[(Packet Cache)] m_get(), m_gethdr()
88 * [(Cluster Cache)] [ Secondary ] [ (Mbuf Cache) ]
89 * [ Cluster Zone ] [ Zone ] [ Mbuf Primary Zone ]
91 * [ Cluster Keg ] \ /
93 * [ Cluster Slabs ] |
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