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/linux/include/uapi/linux/
H A Datmioc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /* atmioc.h - ranges for ATM-related ioctl numbers */
4 /* Written 1995-1999 by Werner Almesberger, EPFL LRC/ICA */
8 * See https://icawww1.epfl.ch/linux-atm/magic.html for the complete list of
19 #define ATMIOC_PHYCOM 0x00 /* PHY device common ioctls, globally unique */
21 #define ATMIOC_PHYTYP 0x10 /* PHY dev type ioctls, unique per PHY type */
23 #define ATMIOC_PHYPRV 0x30 /* PHY dev private ioctls, unique per driver */
27 #define ATMIOC_SARPRV 0x60 /* SAR dev private ioctls, unique per driver */
31 #define ATMIOC_BACKEND 0x90 /* ATM generic backend ioctls, u. per backend */
33 /* 0xb0-0xbf: Reserved for future use */
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/linux/include/linux/phy/
H A Dphy-lvds.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_lvds - LVDS configuration set
11 * @bits_per_lane_and_dclk_cycle: Number of bits per lane per differential
18 * @is_slave: Boolean, true if the phy is a slave
20 * phy to support dual link transmission,
21 * otherwise a regular phy or a master phy.
23 * This structure is used to represent the configuration state of a LVDS phy.
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-msm8996.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include "phy-qcom-qmp-common.h"
24 #include "phy-qcom-qmp.h"
36 /* set of registers with offsets different per-PHY */
139 /* struct qmp_phy_cfg - per-PHY initialization config */
144 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
169 * struct qmp_phy - per-lane phy descriptor
171 * @phy: generic phy
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H A Dphy-qcom-usb-hs-28nm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2018, Linux Foundation. All rights reserved.
4 * Copyright (c) 2018-2020, Linaro Limited
14 #include <linux/phy/phy.h>
20 /* PHY register and bit definitions */
68 static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode, in qcom_snps_hsphy_set_mode() argument
71 struct hsphy_priv *priv = phy_get_drvdata(phy); in qcom_snps_hsphy_set_mode()
73 priv->mode = PHY_MODE_INVALID; in qcom_snps_hsphy_set_mode()
76 priv->mode = mode; in qcom_snps_hsphy_set_mode()
86 val = readb(priv->base + PHY_INTR_CLEAR0); in qcom_snps_hsphy_enable_hv_interrupts()
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/linux/Documentation/devicetree/bindings/net/
H A Dmarvell,pp2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
37 - description: main controller clock
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H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
16 MDIO bus must have a list of child nodes, one per device on the
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
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H A Dqcom-emac.txt4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
6 phandle points to the external PHY node.
11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
16 - internal-phy : phandle to the internal PHY node
17 - phy-handle : phandle to the external PHY node
19 Internal PHY node:
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/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt3 EMIF - External Memory Interface - is an SDRAM controller used in
11 - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
14 "ti,emif-am3352"
15 "ti,emif-am4372"
16 "ti,emif-dra7xx"
17 "ti,emif-keystone"
19 - phy-type : <u32> indicating the DDR phy type. Following are the
21 <1> : Attila PHY
22 <2> : Intelli PHY
24 - device-handle : phandle to a "lpddr2" node representing the memory part
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/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-h3-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun6i-rtc.h>
44 #include <dt-bindings/clock/sun8i-de2.h>
45 #include <dt-bindings/clock/sun8i-h3-ccu.h>
46 #include <dt-bindings/clock/sun8i-r-ccu.h>
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
49 #include <dt-bindings/reset/sun8i-h3-ccu.h>
50 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 interrupt-parent = <&gic>;
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/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,rk3399-pcie-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,rk3399-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip RK3399 PCIE PHY
10 - Heiko Stuebner <heiko@sntech.de>
14 const: rockchip,rk3399-pcie-phy
16 '#phy-cells':
18 - const: 0
20 - const: 1
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H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8MQ USB3 PHY
10 - Li Jun <jun.li@nxp.com>
15 - enum:
16 - fsl,imx8mq-usb-phy
17 - fsl,imx8mp-usb-phy
18 - items:
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H A Dqcom,msm8996-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (MSM8996 PCIe)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
18 const: qcom,msm8996-qmp-pcie-phy
22 - description: serdes
24 "#address-cells":
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/linux/Documentation/networking/dsa/
H A Ddsa.rst22 An Ethernet switch typically comprises multiple front-panel ports and one
27 gateways, or even top-of-rack switches. This host Ethernet controller will
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
52 on Port-based VLAN IDs).
57 - the "cpu" port is the Ethernet switch facing side of the management
61 - the "dsa" port(s) are just conduits between two or more switches, and as such
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx35.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include "imx35-pinfunc.h"
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
38 #address-cells = <1>;
39 #size-cells = <0>;
42 compatible = "arm,arm1136jf-s";
48 avic: avic-interrupt-controller@68000000 {
49 compatible = "fsl,imx35-avic", "fsl,avic";
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/reset/imx8mp-reset-audiomix.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interconnect/fsl,imx8mp.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/thermal/thermal.h>
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/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dxmit.h1 /* SPDX-License-Identifier: GPL-2.0 */
29 __le16 phy_ctl; /* PHY TX control */
70 /* PHY TX control word */
94 u8 phy_stat; /* PHY TX status */
134 __le16 phy_status0; /* PHY RX Status 0 */
135 __u8 jssi; /* PHY RX Status 1: JSSI */
136 __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
137 PAD_BYTES(2); /* PHY RX Status 2 */
138 __le16 phy_status3; /* PHY RX Status 3 */
145 /* PHY RX Status 0 */
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/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dcommon.h2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
44 #define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ##__VA_ARGS__)
45 #define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ##__VA_ARGS__)
46 #define CH_ALERT(adap, fmt, ...) dev_alert(&adap->pdev->dev, fmt, ##__VA_ARGS__)
53 if ((adapter)->msg_enable & NETIF_MSG_##category) \
54 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
92 enum { /* adapter interrupt-maintained statistics */
124 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.h1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
83 #define SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
84 /* Single Media board contains single external phy */
85 #define SINGLE_MEDIA(params) (params->num_phys == 2)
86 /* Dual Media board contains two external phy with different media */
87 #define DUAL_MEDIA(params) (params->num_phys == 3)
118 /* Same configuration is shared between the XGXS and the first external phy */
119 #define LINK_CONFIG_SIZE (MAX_PHYS - 1)
121 0 : (_phy_idx - 1))
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/linux/Documentation/devicetree/bindings/pci/
H A Dspear13xx-pcie.txt4 SPEAr13XX uses the Synopsys DesignWare PCIe controller and ST MiPHY as PHY
8 - compatible : should be "st,spear1340-pcie", "snps,dw-pcie".
9 - phys : phandle to PHY node associated with PCIe controller
10 - phy-names : must be "pcie-phy"
11 - All other definitions as per generic PCI bindings
14 - st,pcie-is-gen1 indicates that forced gen1 initialization is needed.
/linux/Documentation/devicetree/bindings/media/
H A Dcdns,csi2tx.txt1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
20 - phy-names: must contain "dphy"
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/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Dcoex.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2023-2024 Intel Corporation
4 * Copyright (C) 2013-2014, 2018-2019 Intel Corporation
5 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
14 #define BITS(nb) (BIT(nb) - 1)
43 * struct iwl_bt_coex_cmd - bt coex configuration command
64 * struct iwl_bt_coex_ci_cmd - bt coex channel inhibition command
66 * @primary_ch_phy_id: primary channel PHY ID
68 * @secondary_ch_phy_id: secondary channel PHY ID
98 * struct iwl_bt_coex_prof_old_notif - notification about BT coex
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/linux/Documentation/devicetree/bindings/usb/
H A Dti,keystone-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Quadros <rogerq@kernel.org>
15 - enum:
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
22 '#address-cells':
25 '#size-cells':
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/linux/drivers/scsi/mpt3sas/
H A Dmpt3sas_scsih.c5 * Copyright (C) 2012-2014 LSI Corporation
6 * Copyright (C) 2013-2014 Avago Technologies
7 * (mailto: MPT-FusionLinux.pdl@avagotech.com)
22 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
41 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
93 static u8 scsi_io_cb_idx = -1;
94 static u8 tm_cb_idx = -1;
95 static u8 ctl_cb_idx = -1;
96 static u8 base_cb_idx = -1;
97 static u8 port_enable_cb_idx = -1;
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/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
12 #include "emac-mac.h"
13 #include "emac-phy.h"
14 #include "emac-sgmii.h"
176 /* SGMII v2 per lane registers */
179 /* SGMII v2 PHY common registers */
183 /* SGMII v2 PHY registers per lane */
225 u64 rx_sz_65_127; /* packets that are 65-127 bytes */
226 u64 rx_sz_128_255; /* packets that are 128-255 bytes */
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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/
16 #include <sound/omap-hdmi-audio.h>
68 /* HDMI PHY */
168 u32 y_res; /* Line per panel */
169 u32 x_res; /* pixel per line */
305 /* HDMI PHY funcs */
306 int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,
308 void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
309 int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
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