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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046-post.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2015-2016 Freescale Semiconductor Inc.
12 #include "qoriq-fman3-0.dtsi"
13 #include "qoriq-fman3-0-1g-0.dtsi"
14 #include "qoriq-fman3-0-1g-1.dtsi"
15 #include "qoriq-fman3-0-1g-2.dtsi"
16 #include "qoriq-fman3-0-1g-3.dtsi"
17 #include "qoriq-fman3-0-1g-4.dtsi"
18 #include "qoriq-fman3-0-1g-5.dtsi"
19 #include "qoriq-fman3-0-10g-0.dtsi"
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H A Dfsl-ls1043-post.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2015-2016 Freescale Semiconductor Inc.
11 #include "qoriq-fman3-0.dtsi"
12 #include "qoriq-fman3-0-1g-0.dtsi"
13 #include "qoriq-fman3-0-1g-1.dtsi"
14 #include "qoriq-fman3-0-1g-2.dtsi"
15 #include "qoriq-fman3-0-1g-3.dtsi"
16 #include "qoriq-fman3-0-1g-4.dtsi"
17 #include "qoriq-fman3-0-1g-5.dtsi"
18 #include "qoriq-fman3-0-10g-0.dtsi"
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H A Dtqmls1088a-mbls10xxa-mc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
10 #include <dt-bindings/net/ti-dp83867.h>
15 i2c-bus = <&sfp1_i2c>;
16 mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>;
17 los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>;
18 tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>;
19 tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>;
24 i2c-bus = <&sfp2_i2c>;
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H A Dfsl-ls1088a-rdb.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2017-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
17 compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
21 phy-handle = <&mdio2_aquantia_phy>;
22 phy-connection-type = "10gbase-r";
23 pcs-handle = <&pcs2>;
27 phy-handle = <&mdio1_phy5>;
28 phy-connection-type = "qsgmii";
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H A Dfsl-ls1088a-ten64.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
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H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
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H A Dethernet-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 local-mac-address:
22 $ref: /schemas/types.yaml#/definitions/uint8-array
26 mac-address:
31 local-mac-address property.
32 $ref: /schemas/types.yaml#/definitions/uint8-array
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
42 - description: Ethernet core interrupt
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H A Dfsl,qoriq-mc-dpmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ioana Ciornei <ioana.ciornei@nxp.com>
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
17 - $ref: ethernet-controller.yaml#
21 const: fsl,qoriq-mc-dpmac
27 pcs-handle:
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H A Drenesas,rzn1-gmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzn1-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Romain Gantois <romain.gantois@bootlin.com>
17 - renesas,r9a06g032-gmac
18 - renesas,rzn1-gmac
20 - compatible
23 - $ref: snps,dwmac.yaml#
28 - enum:
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/linux/Documentation/networking/
H A Dsfp-phylink.rst1 .. SPDX-License-Identifier: GPL-2.0
10 phylink is a mechanism to support hot-pluggable networking modules
11 directly connected to a MAC without needing to re-initialise the
12 adapter on hot-plug events.
14 phylink supports conventional phylib-based setups, fixed link setups
35 3. In-band mode
37 In-band mode is used with 802.3z, SGMII and similar interface modes,
38 and we are expecting to use and honor the in-band negotiation or
43 .. code-block:: none
47 phy-mode = "sgmii";
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Drenesas,rzn1-a5psw.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clément Léger <clement.leger@bootlin.com>
17 - $ref: dsa.yaml#/$defs/ethernet-ports
22 - enum:
23 - renesas,r9a06g032-a5psw
24 - const: renesas,rzn1-a5psw
31 - description: Device Level Ring (DLR) interrupt
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/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-0-10g-1-best-effort.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
41 fsl,fman-best-effort-port;
45 cell-index = <0x29>;
46 compatible = "fsl,fman-v3-port-tx";
48 fsl,fman-10g-port;
49 fsl,fman-best-effort-port;
53 cell-index = <1>;
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H A Dqoriq-fman3-1-10g-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x10>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x30>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
51 cell-index = <0x8>;
52 compatible = "fsl,fman-memac";
54 fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
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H A Dqoriq-fman3-0-10g-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x10>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x30>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
51 cell-index = <0x8>;
52 compatible = "fsl,fman-memac";
54 fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
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H A Dqoriq-fman3-0-10g-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x11>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x31>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
51 cell-index = <0x9>;
52 compatible = "fsl,fman-memac";
54 fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
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H A Dqoriq-fman3-1-10g-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x11>;
38 compatible = "fsl,fman-v3-port-rx";
40 fsl,fman-10g-port;
44 cell-index = <0x31>;
45 compatible = "fsl,fman-v3-port-tx";
47 fsl,fman-10g-port;
51 cell-index = <0x9>;
52 compatible = "fsl,fman-memac";
54 fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
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H A Dqoriq-fman3-1-1g-3.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xb>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2b>;
44 compatible = "fsl,fman-v3-port-tx";
49 cell-index = <3>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
53 ptp-timer = <&ptp_timer1>;
54 pcsphy-handle = <&pcsphy11>, <&qsgmiic_pcs3>;
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H A Dqoriq-fman3-0-1g-3.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xb>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2b>;
44 compatible = "fsl,fman-v3-port-tx";
49 cell-index = <3>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
53 ptp-timer = <&ptp_timer0>;
54 pcsphy-handle = <&pcsphy3>, <&qsgmiia_pcs3>;
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H A Dqoriq-fman3-1-1g-5.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xd>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2d>;
44 compatible = "fsl,fman-v3-port-tx";
49 cell-index = <5>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
53 ptp-timer = <&ptp_timer1>;
54 pcsphy-handle = <&pcsphy13>, <&qsgmiid_pcs1>;
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H A Dqoriq-fman3-1-1g-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x29>;
44 compatible = "fsl,fman-v3-port-tx";
49 cell-index = <1>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
53 ptp-timer = <&ptp_timer1>;
54 pcsphy-handle = <&pcsphy9>, <&qsgmiic_pcs1>;
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H A Dqoriq-fman3-1-1g-2.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xa>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2a>;
44 compatible = "fsl,fman-v3-port-tx";
49 cell-index = <2>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
53 ptp-timer = <&ptp_timer1>;
54 pcsphy-handle = <&pcsphy10>, <&qsgmiic_pcs2>;
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H A Dqoriq-fman3-0-1g-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0x9>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x29>;
44 compatible = "fsl,fman-v3-port-tx";
49 cell-index = <1>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
53 ptp-timer = <&ptp_timer0>;
54 pcsphy-handle = <&pcsphy1>, <&qsgmiia_pcs1>;
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H A Dqoriq-fman3-0-1g-2.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
37 cell-index = <0xa>;
38 compatible = "fsl,fman-v3-port-rx";
43 cell-index = <0x2a>;
44 compatible = "fsl,fman-v3-port-tx";
49 cell-index = <2>;
50 compatible = "fsl,fman-memac";
52 fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
53 ptp-timer = <&ptp_timer0>;
54 pcsphy-handle = <&pcsphy2>, <&qsgmiia_pcs2>;
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