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/linux/drivers/clk/x86/
H A Dclk-pmc-atom.c154 struct clk_plt *pclk; in plt_clk_register() local
158 pclk = devm_kzalloc(&pdev->dev, sizeof(*pclk), GFP_KERNEL); in plt_clk_register()
159 if (!pclk) in plt_clk_register()
168 pclk->hw.init = &init; in plt_clk_register()
169 pclk->reg = pmc_data->base + PMC_CLK_CTL_OFFSET + id * PMC_CLK_CTL_SIZE; in plt_clk_register()
170 spin_lock_init(&pclk->lock); in plt_clk_register()
177 if (pmc_data->critical && plt_clk_is_enabled(&pclk->hw)) in plt_clk_register()
180 ret = devm_clk_hw_register(&pdev->dev, &pclk->hw); in plt_clk_register()
182 pclk = ERR_PTR(ret); in plt_clk_register()
186 pclk->lookup = clkdev_hw_create(&pclk->hw, init.name, NULL); in plt_clk_register()
[all …]
/linux/drivers/clocksource/
H A Dtimer-microchip-pit64b.c53 * @pclk: PIT64B's peripheral clock
59 struct clk *pclk; member
140 clk_disable_unprepare(timer->pclk); in mchp_pit64b_suspend()
145 clk_prepare_enable(timer->pclk); in mchp_pit64b_resume()
261 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
262 * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate
263 * could be changed via clock APIs. The chosen clock (pclk or gclk) could be
268 * requested rate. If PCLK/GCLK < 3 (condition requested by PIT64B hardware)
269 * then the function falls back on using PCLK as clock source for PIT64B timer
280 * | |-->pclk -->|-->| | +---------+ +-----+ |
[all …]
H A Dtimer-rockchip.c37 struct clk *pclk; member
131 struct clk *pclk; in rk_timer_probe() local
146 pclk = of_clk_get_by_name(np, "pclk"); in rk_timer_probe()
147 if (IS_ERR(pclk)) { in rk_timer_probe()
148 ret = PTR_ERR(pclk); in rk_timer_probe()
149 pr_err("Failed to get pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
153 ret = clk_prepare_enable(pclk); in rk_timer_probe()
155 pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME); in rk_timer_probe()
158 timer->pclk = pclk; in rk_timer_probe()
191 clk_disable_unprepare(pclk); in rk_timer_probe()
[all …]
H A Ddw_apb_timer_of.c21 struct clk *pclk; in timer_get_base_and_rate() local
44 pclk = of_clk_get_by_name(np, "pclk"); in timer_get_base_and_rate()
45 if (!IS_ERR(pclk)) in timer_get_base_and_rate()
46 if (clk_prepare_enable(pclk)) in timer_get_base_and_rate()
47 pr_warn("pclk for %pOFn is present, but could not be activated\n", in timer_get_base_and_rate()
77 if (!IS_ERR(pclk)) { in timer_get_base_and_rate()
78 clk_disable_unprepare(pclk); in timer_get_base_and_rate()
79 clk_put(pclk); in timer_get_base_and_rate()
/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1383 #define PCLK(_id, _name, _parent, _flags, _mgate)\ macro
1887 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1888 PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1889 PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1890 PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1891 PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1892 PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1893 PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1894 PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1895 PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
[all …]
/linux/drivers/clk/samsung/
H A Dclk-s3c64xx.c164 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
221 GATE_ON(PCLK_SKEY, "pclk_skey", "pclk", PCLK_GATE, 24),
222 GATE_ON(PCLK_CHIPID, "pclk_chipid", "pclk", PCLK_GATE, 23),
223 GATE_BUS(PCLK_SPI1, "pclk_spi1", "pclk", PCLK_GATE, 22),
224 GATE_BUS(PCLK_SPI0, "pclk_spi0", "pclk", PCLK_GATE, 21),
225 GATE_BUS(PCLK_HSIRX, "pclk_hsirx", "pclk", PCLK_GATE, 20),
226 GATE_BUS(PCLK_HSITX, "pclk_hsitx", "pclk", PCLK_GATE, 19),
227 GATE_ON(PCLK_GPIO, "pclk_gpio", "pclk", PCLK_GATE, 18),
228 GATE_BUS(PCLK_IIC0, "pclk_iic0", "pclk", PCLK_GATE, 17),
229 GATE_BUS(PCLK_IIS1, "pclk_iis1", "pclk", PCLK_GATE, 16),
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dversatile-ab.dts160 pclk: clock-pclk { label
235 clocks = <&pclk>;
243 clocks = <&xtal24mhz>, <&pclk>;
251 clocks = <&xtal24mhz>, <&pclk>;
259 clocks = <&xtal24mhz>, <&pclk>;
266 clocks = <&pclk>;
273 clocks = <&pclk>;
281 clocks = <&osc1>, <&pclk>;
320 clocks = <&pclk>;
328 clocks = <&pclk>;
[all …]
H A Darm-realview-eb.dtsi71 pclk: clock-pclk { label
289 clocks = <&pclk>;
302 clocks = <&mclk>, <&pclk>;
312 clocks = <&kmiclk>, <&pclk>;
319 clocks = <&kmiclk>, <&pclk>;
326 clocks = <&pclk>;
333 clocks = <&uartclk>, <&pclk>;
340 clocks = <&uartclk>, <&pclk>;
347 clocks = <&uartclk>, <&pclk>;
354 clocks = <&uartclk>, <&pclk>;
[all …]
H A Darm-realview-pbx.dtsi86 pclk: clock-pclk { label
331 clocks = <&uartclk>, <&pclk>;
338 clocks = <&uartclk>, <&pclk>;
345 clocks = <&uartclk>, <&pclk>;
352 clocks = <&sspclk>, <&pclk>;
359 clocks = <&wdogclk>, <&pclk>;
367 clocks = <&wdogclk>, <&pclk>;
377 <&pclk>;
388 <&pclk>;
401 clocks = <&pclk>;
[all …]
H A Darm-realview-pb1176.dts81 pclk: clock-pclk { label
339 clocks = <&timclk>, <&timclk>, <&pclk>;
349 clocks = <&timclk>, <&timclk>, <&pclk>;
358 clocks = <&pclk>;
371 clocks = <&pclk>;
380 clocks = <&sspclk>, <&pclk>;
389 clocks = <&uartclk>, <&pclk>;
398 clocks = <&uartclk>, <&pclk>;
407 clocks = <&uartclk>, <&pclk>;
416 clocks = <&uartclk>, <&pclk>;
[all …]
H A Darm-realview-pb11mp.dts187 pclk: clock-pclk { label
436 clocks = <&pclk>;
451 clocks = <&mclk>, <&pclk>;
463 clocks = <&kmiclk>, <&pclk>;
472 clocks = <&kmiclk>, <&pclk>;
481 clocks = <&uartclk>, <&pclk>;
490 clocks = <&uartclk>, <&pclk>;
499 clocks = <&uartclk>, <&pclk>;
508 clocks = <&uartclk>, <&pclk>;
517 clocks = <&sspclk>, <&pclk>;
[all …]
H A Dintegratorcp.dts80 pclk: clock-pclk { label
243 clocks = <&pclk>;
249 clocks = <&uartclk>, <&pclk>;
255 clocks = <&uartclk>, <&pclk>;
261 clocks = <&kmiclk>, <&pclk>;
267 clocks = <&kmiclk>, <&pclk>;
279 clocks = <&uartclk>, <&pclk>;
287 clocks = <&pclk>;
295 clocks = <&auxosc>, <&pclk>;
/linux/drivers/clk/hisilicon/
H A Dclk-hi3620.c34 static const char *const uart0_mux_p[] __initconst = { "osc26m", "pclk", };
35 static const char *const uart1_mux_p[] __initconst = { "osc26m", "pclk", };
36 static const char *const uart2_mux_p[] __initconst = { "osc26m", "pclk", };
37 static const char *const uart3_mux_p[] __initconst = { "osc26m", "pclk", };
38 static const char *const uart4_mux_p[] __initconst = { "osc26m", "pclk", };
68 { HI3620_PCLK, "pclk", NULL, 0, 26000000, },
137 { HI3620_RTCCLK, "rtcclk", "pclk", CLK_SET_RATE_PARENT, 0x20, 5, 0, },
138 { HI3620_KPC_CLK, "kpc_clk", "pclk", CLK_SET_RATE_PARENT, 0x20, 6, 0, },
139 { HI3620_GPIOCLK0, "gpioclk0", "pclk", CLK_SET_RATE_PARENT, 0x20, 8, 0, },
140 { HI3620_GPIOCLK1, "gpioclk1", "pclk", CLK_SET_RATE_PARENT, 0x20, 9, 0, },
[all …]
/linux/arch/arm/boot/dts/calxeda/
H A Decx-common.dtsi50 clocks = <&pclk>;
60 clocks = <&pclk>;
71 clocks = <&pclk>;
82 clocks = <&pclk>;
93 clocks = <&pclk>;
102 clocks = <&pclk>;
110 clocks = <&pclk>;
118 clocks = <&pclk>, <&pclk>;
187 pclk: pclk { label
199 clocks = <&pclk>;
/linux/drivers/pwm/
H A Dpwm-rockchip.c34 struct clk *pclk; member
70 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
97 clk_disable(pc->pclk); in rockchip_pwm_get_state()
194 ret = clk_enable(pc->pclk); in rockchip_pwm_apply()
222 clk_disable(pc->pclk); in rockchip_pwm_apply()
324 pc->pclk = devm_clk_get(&pdev->dev, "pclk"); in rockchip_pwm_probe()
326 pc->pclk = pc->clk; in rockchip_pwm_probe()
328 if (IS_ERR(pc->pclk)) in rockchip_pwm_probe()
329 return dev_err_probe(&pdev->dev, PTR_ERR(pc->pclk), "Can't get APB clk\n"); in rockchip_pwm_probe()
335 ret = clk_prepare_enable(pc->pclk); in rockchip_pwm_probe()
[all …]
/linux/drivers/rtc/
H A Drtc-ftrtc010.c34 struct clk *pclk; member
123 rtc->pclk = devm_clk_get(dev, "PCLK"); in ftrtc010_rtc_probe()
124 if (IS_ERR(rtc->pclk)) { in ftrtc010_rtc_probe()
125 dev_err(dev, "could not get PCLK\n"); in ftrtc010_rtc_probe()
127 ret = clk_prepare_enable(rtc->pclk); in ftrtc010_rtc_probe()
129 dev_err(dev, "failed to enable PCLK\n"); in ftrtc010_rtc_probe()
190 clk_disable_unprepare(rtc->pclk); in ftrtc010_rtc_probe()
200 if (!IS_ERR(rtc->pclk)) in ftrtc010_rtc_remove()
201 clk_disable_unprepare(rtc->pclk); in ftrtc010_rtc_remove()
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi40 clocks = <&timclk>, <&pclk>;
49 clocks = <&timclk>, <&pclk>;
64 clocks = <&pclk>;
78 clocks = <&pclk>;
92 clocks = <&pclk>;
107 clocks = <&pclk>;
232 /* The PCLK domain uses HCLK right off */
233 pclk: pclk@0 { label
332 clocks = <&pclk>;
338 clocks = <&pclk>;
[all …]
/linux/drivers/clk/
H A Dclk-conf.c19 struct clk *clk, *pclk; in __set_clk_parents() local
41 pclk = of_clk_get_from_provider(&clkspec); in __set_clk_parents()
43 if (IS_ERR(pclk)) { in __set_clk_parents()
44 if (PTR_ERR(pclk) != -EPROBE_DEFER) in __set_clk_parents()
47 return PTR_ERR(pclk); in __set_clk_parents()
69 rc = clk_set_parent(clk, pclk); in __set_clk_parents()
72 __clk_get_name(clk), __clk_get_name(pclk), rc); in __set_clk_parents()
74 clk_put(pclk); in __set_clk_parents()
78 clk_put(pclk); in __set_clk_parents()
/linux/arch/riscv/boot/dts/canaan/
H A Dk210.dtsi259 clock-names = "ssi_clk", "pclk";
300 clock-names = "ref", "pclk";
311 clock-names = "ref", "pclk";
322 clock-names = "ref", "pclk";
332 clock-names = "ref", "pclk";
343 clock-names = "timer", "pclk";
353 clock-names = "timer", "pclk";
363 clock-names = "timer", "pclk";
373 clock-names = "timer", "pclk";
383 clock-names = "timer", "pclk";
[all …]
/linux/drivers/hwtracing/coresight/
H A Dcoresight-tpiu.c57 * @pclk: APB clock if present, otherwise NULL
63 struct clk *pclk; member
154 drvdata->pclk = coresight_get_enable_apb_pclk(dev); in __tpiu_probe()
155 if (IS_ERR(drvdata->pclk)) in __tpiu_probe()
218 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) in tpiu_runtime_suspend()
219 clk_disable_unprepare(drvdata->pclk); in tpiu_runtime_suspend()
230 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) in tpiu_runtime_resume()
231 clk_prepare_enable(drvdata->pclk); in tpiu_runtime_resume()
296 if (!IS_ERR_OR_NULL(drvdata->pclk)) in tpiu_platform_remove()
297 clk_put(drvdata->pclk); in tpiu_platform_remove()
H A Dcoresight-replicator.c34 * @pclk: APB clock if present, otherwise NULL
42 struct clk *pclk; member
248 drvdata->pclk = coresight_get_enable_apb_pclk(dev); in replicator_probe()
249 if (IS_ERR(drvdata->pclk)) in replicator_probe()
298 if (ret && !IS_ERR_OR_NULL(drvdata->pclk)) in replicator_probe()
299 clk_disable_unprepare(drvdata->pclk); in replicator_probe()
337 if (!IS_ERR_OR_NULL(drvdata->pclk)) in replicator_platform_remove()
338 clk_put(drvdata->pclk); in replicator_platform_remove()
349 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) in replicator_runtime_suspend()
350 clk_disable_unprepare(drvdata->pclk); in replicator_runtime_suspend()
[all …]
H A Dcoresight-funnel.c39 * @pclk: APB clock if present, otherwise NULL
47 struct clk *pclk; member
241 drvdata->pclk = coresight_get_enable_apb_pclk(dev); in funnel_probe()
242 if (IS_ERR(drvdata->pclk)) in funnel_probe()
286 if (ret && !IS_ERR_OR_NULL(drvdata->pclk)) in funnel_probe()
287 clk_disable_unprepare(drvdata->pclk); in funnel_probe()
308 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) in funnel_runtime_suspend()
309 clk_disable_unprepare(drvdata->pclk); in funnel_runtime_suspend()
321 if (drvdata && !IS_ERR_OR_NULL(drvdata->pclk)) in funnel_runtime_resume()
322 clk_prepare_enable(drvdata->pclk); in funnel_runtime_resume()
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12.dtsi58 clock-names = "pclk", "dclk", "sysclk";
86 clock-names = "pclk",
207 clock-names = "pclk", "sclk", "sclk_sel",
222 clock-names = "pclk", "sclk", "sclk_sel",
237 clock-names = "pclk", "sclk", "sclk_sel",
252 clock-names = "pclk", "sclk", "sclk_sel",
266 clock-names = "pclk", "refclk";
279 clock-names = "pclk", "mclk";
294 clock-names = "pclk", "sclk", "sclk_sel",
309 clock-names = "pclk", "sclk", "sclk_sel",
[all …]
/linux/sound/soc/meson/
H A Daiu.c86 return clk_prepare_enable(aiu->i2s.clks[PCLK].clk); in aiu_cpu_component_probe()
93 clk_disable_unprepare(aiu->i2s.clks[PCLK].clk); in aiu_cpu_component_remove()
200 [PCLK] = "i2s_pclk",
207 [PCLK] = "spdif_pclk",
215 struct clk *pclk; in aiu_clk_get() local
218 pclk = devm_clk_get_enabled(dev, "pclk"); in aiu_clk_get()
219 if (IS_ERR(pclk)) in aiu_clk_get()
220 return dev_err_probe(dev, PTR_ERR(pclk), "Can't get the aiu pclk\n"); in aiu_clk_get()
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_common.c52 int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts) in hdmi_compute_acr() argument
75 if (pclk == 27027000 || pclk == 74250000) in hdmi_compute_acr()
78 if (pclk == 27027000) in hdmi_compute_acr()
85 if (pclk == 27027000) in hdmi_compute_acr()
146 *cts = (pclk/1000) * (*n / 128) * deep_color / (sample_freq / 10); in hdmi_compute_acr()

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