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Searched full:pclk (Results 1 – 17 of 17) sorted by relevance

/illumos-gate/usr/src/uts/sun/sys/
H A Dser_async.h54 #define ZSPEED(n) ZSTimeConst(PCLK, n)
H A Dzsdev.h77 #define PCLK (19660800/4) /* basic clock rate for UARTs */ macro
H A Dser_zscc.h228 #define ZSWR14_BAUD_FROM_PCLK 0x02 /* Baud rate gen src = PCLK not RTxC */
/illumos-gate/usr/src/uts/sun/io/
H A Dzs_hdlc.c1976 tconst = (PCLK + speed) / (2 * speed) - 2; in zsh_program()
1982 sm->sm_baudrate = PCLK / (2 * ((int)tconst + 2)); in zsh_program()
1989 tconst = (PCLK + speed) / (2 * speed) - 2; in zsh_program()
1997 speed = PCLK / (2 * ((int)tconst + 2)); in zsh_program()
/illumos-gate/usr/src/uts/sun4u/sunfire/io/
H A Dsysctrl.c3293 { 0x0e, 0x02 }, /* BR generator comes from Z-SCC's PCLK input */
3296 { 0x0e, 0x03 }, /* BR comes from PCLK, BR generator is enabled */
/illumos-gate/usr/src/data/perfmon/JKT/
H A DJaketown_uncore_V20.json1171 "BriefDescription": "pclk Cycles",
1172 …0 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. …
/illumos-gate/usr/src/data/perfmon/BDW-DE/
H A Dbroadwellde_uncore_v7.json9965 "BriefDescription": "pclk Cycles",
9966 …1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. …
/illumos-gate/usr/src/data/perfmon/IVT/
H A Divytown_uncore_v20.json7111 "BriefDescription": "pclk Cycles",
7112 …0 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. …
/illumos-gate/usr/src/data/perfmon/BDX/
H A Dbroadwellx_uncore_v17.json5779 "BriefDescription": "pclk Cycles",
5780 …1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. …
/illumos-gate/usr/src/data/perfmon/HSX/
H A Dhaswellx_uncore_v22.json6209 "BriefDescription": "pclk Cycles",
6210 …0 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. …
/illumos-gate/usr/src/data/perfmon/CLX/
H A Dcascadelakex_uncore_v1.11_experimental.json47548 "BriefDescription": "pclk Cycles",
47549 …1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. …
/illumos-gate/usr/src/data/perfmon/SKX/
H A Dskylakex_uncore_v1.24_experimental.json47332 "BriefDescription": "pclk Cycles",
47333 …1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. …
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A Dreg_addr_ah_compile15.h33717 … (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free running ext…
33866 … 0x054360UL //Access:RW DataWidth:0x14 Sampling interval * pclk, 2ns to 2ms. Chips…
33868 …ccess:RW DataWidth:0x18 If greater than 0, delay trigger count value * pclk, 0 to 32ms Chips: …
55036 … 0x6a0244UL //Access:RW DataWidth:0x14 Debug only: Sampling interval * pclk, 2ns to 2ms. Chips…
55038 …ataWidth:0x18 Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms Chips: …
55484 … 0x700144UL //Access:RW DataWidth:0x14 Debug only: Sampling interval * pclk, 2ns to 2ms. Chips…
55486 …ataWidth:0x18 Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms Chips: …
H A Dreg_addr_e5.h37060 … (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free running ext…
37209 … 0x054360UL //Access:RW DataWidth:0x14 // Sampling interval * pclk, 2ns to 2ms.
37211 …UL //Access:RW DataWidth:0x18 // If greater than 0, delay trigger count value * pclk, 0 to 32ms
58294 … 0x6a0244UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
58296 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
58798 … 0x700144UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
58800 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
H A Dreg_addr_k2.h37060 … (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free running ext…
37209 … 0x054360UL //Access:RW DataWidth:0x14 // Sampling interval * pclk, 2ns to 2ms.
37211 …UL //Access:RW DataWidth:0x18 // If greater than 0, delay trigger count value * pclk, 0 to 32ms
58294 … 0x6a0244UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
58296 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
58798 … 0x700144UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
58800 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
H A Dreg_addr_bb.h37060 … (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free running ext…
37209 … 0x054360UL //Access:RW DataWidth:0x14 // Sampling interval * pclk, 2ns to 2ms.
37211 …UL //Access:RW DataWidth:0x18 // If greater than 0, delay trigger count value * pclk, 0 to 32ms
58294 … 0x6a0244UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
58296 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
58798 … 0x700144UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
58800 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
H A Dreg_addr.h37130 … (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free running ext…
37279 … 0x054360UL //Access:RW DataWidth:0x14 // Sampling interval * pclk, 2ns to 2ms.
37281 …UL //Access:RW DataWidth:0x18 // If greater than 0, delay trigger count value * pclk, 0 to 32ms
60439 … 0x6a0244UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
60441 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms
60943 … 0x700144UL //Access:RW DataWidth:0x14 // Debug only: Sampling interval * pclk, 2ns to 2ms.
60945 …RW DataWidth:0x18 // Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms