xref: /linux/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml (revision 2f2c7254931f41b5736e3ba12aaa9ac1bbeeeb92) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32MP25 PCIe Endpoint
8
9maintainers:
10  - Christian Bruel <christian.bruel@foss.st.com>
11
12description:
13  PCIe endpoint controller based on the Synopsys DesignWare PCIe core.
14
15allOf:
16  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
17  - $ref: /schemas/pci/st,stm32-pcie-common.yaml#
18
19properties:
20  compatible:
21    const: st,stm32mp25-pcie-ep
22
23  reg:
24    items:
25      - description: Data Bus Interface (DBI) registers.
26      - description: Data Bus Interface (DBI) shadow registers.
27      - description: Internal Address Translation Unit (iATU) registers.
28      - description: PCIe configuration registers.
29
30  reg-names:
31    items:
32      - const: dbi
33      - const: dbi2
34      - const: atu
35      - const: addr_space
36
37  reset-gpios:
38    description: GPIO controlled connection to PERST# signal
39    maxItems: 1
40
41  phys:
42    maxItems: 1
43
44required:
45  - phys
46  - reset-gpios
47
48unevaluatedProperties: false
49
50examples:
51  - |
52    #include <dt-bindings/clock/st,stm32mp25-rcc.h>
53    #include <dt-bindings/gpio/gpio.h>
54    #include <dt-bindings/phy/phy.h>
55    #include <dt-bindings/reset/st,stm32mp25-rcc.h>
56
57    pcie-ep@48400000 {
58        compatible = "st,stm32mp25-pcie-ep";
59        reg = <0x48400000 0x400000>,
60              <0x48500000 0x100000>,
61              <0x48700000 0x80000>,
62              <0x10000000 0x10000000>;
63        reg-names = "dbi", "dbi2", "atu", "addr_space";
64        clocks = <&rcc CK_BUS_PCIE>;
65        phys = <&combophy PHY_TYPE_PCIE>;
66        resets = <&rcc PCIE_R>;
67        pinctrl-names = "default", "init";
68        pinctrl-0 = <&pcie_pins_a>;
69        pinctrl-1 = <&pcie_init_pins_a>;
70        reset-gpios = <&gpioj 8 GPIO_ACTIVE_LOW>;
71        access-controllers = <&rifsc 68>;
72        power-domains = <&CLUSTER_PD>;
73    };
74