1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm X1E80100 PCI Express Root Complex 8 9maintainers: 10 - Bjorn Andersson <andersson@kernel.org> 11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 12 13description: 14 Qualcomm X1E80100 SoC (and compatible) PCIe root complex controller is based on 15 the Synopsys DesignWare PCIe IP. 16 17properties: 18 compatible: 19 const: qcom,pcie-x1e80100 20 21 reg: 22 minItems: 6 23 maxItems: 6 24 25 reg-names: 26 items: 27 - const: parf # Qualcomm specific registers 28 - const: dbi # DesignWare PCIe registers 29 - const: elbi # External local bus interface registers 30 - const: atu # ATU address space 31 - const: config # PCIe configuration space 32 - const: mhi # MHI registers 33 34 clocks: 35 minItems: 6 36 maxItems: 7 37 38 clock-names: 39 minItems: 6 40 items: 41 - const: aux # Auxiliary clock 42 - const: cfg # Configuration clock 43 - const: bus_master # Master AXI clock 44 - const: bus_slave # Slave AXI clock 45 - const: slave_q2a # Slave Q2A clock 46 - const: noc_aggr # Aggre NoC PCIe AXI clock 47 - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock 48 49 interrupts: 50 minItems: 8 51 maxItems: 9 52 53 interrupt-names: 54 minItems: 8 55 items: 56 - const: msi0 57 - const: msi1 58 - const: msi2 59 - const: msi3 60 - const: msi4 61 - const: msi5 62 - const: msi6 63 - const: msi7 64 - const: global 65 66 resets: 67 minItems: 1 68 maxItems: 2 69 70 reset-names: 71 minItems: 1 72 items: 73 - const: pci # PCIe core reset 74 - const: link_down # PCIe link down reset 75 76allOf: 77 - $ref: qcom,pcie-common.yaml# 78 79unevaluatedProperties: false 80 81examples: 82 - | 83 #include <dt-bindings/clock/qcom,x1e80100-gcc.h> 84 #include <dt-bindings/gpio/gpio.h> 85 #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h> 86 #include <dt-bindings/interrupt-controller/arm-gic.h> 87 88 soc { 89 #address-cells = <2>; 90 #size-cells = <2>; 91 92 pcie@1c08000 { 93 compatible = "qcom,pcie-x1e80100"; 94 reg = <0 0x01c08000 0 0x3000>, 95 <0 0x7c000000 0 0xf1d>, 96 <0 0x7c000f40 0 0xa8>, 97 <0 0x7c001000 0 0x1000>, 98 <0 0x7c100000 0 0x100000>, 99 <0 0x01c0b000 0 0x1000>; 100 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 101 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 102 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 103 104 bus-range = <0x00 0xff>; 105 device_type = "pci"; 106 linux,pci-domain = <0>; 107 num-lanes = <2>; 108 109 #address-cells = <3>; 110 #size-cells = <2>; 111 112 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 113 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 114 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 115 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 116 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 117 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>, 118 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>; 119 clock-names = "aux", 120 "cfg", 121 "bus_master", 122 "bus_slave", 123 "slave_q2a", 124 "noc_aggr", 125 "cnoc_sf_axi"; 126 127 dma-coherent; 128 129 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 138 interrupt-names = "msi0", "msi1", "msi2", "msi3", 139 "msi4", "msi5", "msi6", "msi7", "global"; 140 #interrupt-cells = <1>; 141 interrupt-map-mask = <0 0 0 0x7>; 142 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 143 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 144 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 145 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 146 147 interconnects = <&pcie_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 148 <&gem_noc MASTER_APPSS_PROC 0 &cnoc_main SLAVE_PCIE_4 0>; 149 interconnect-names = "pcie-mem", "cpu-pcie"; 150 151 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 152 <0x100 &apps_smmu 0x1401 0x1>; 153 154 phys = <&pcie4_phy>; 155 phy-names = "pciephy"; 156 157 pinctrl-0 = <&pcie0_default_state>; 158 pinctrl-names = "default"; 159 160 power-domains = <&gcc GCC_PCIE_4_GDSC>; 161 162 resets = <&gcc GCC_PCIE_4_BCR>; 163 reset-names = "pci"; 164 165 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 166 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 167 }; 168 }; 169