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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dfsl,imx6q-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe host controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
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H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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H A Dfsl,imx6q-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe Endpoint controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 This PCIe controller is based on the Synopsys DesignWare PCIe IP and
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
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H A Drcar-pci.txt1 * Renesas R-Car PCIe interface
4 compatible: "renesas,pcie-r8a7742" for the R8A7742 SoC;
5 "renesas,pcie-r8a7743" for the R8A7743 SoC;
6 "renesas,pcie-r8a7744" for the R8A7744 SoC;
7 "renesas,pcie-r8a774a1" for the R8A774A1 SoC;
8 "renesas,pcie-r8a774b1" for the R8A774B1 SoC;
9 "renesas,pcie-r8a774c0" for the R8A774C0 SoC;
10 "renesas,pcie-r8a7779" for the R8A7779 SoC;
11 "renesas,pcie-r8a7790" for the R8A7790 SoC;
12 "renesas,pcie-r8a7791" for the R8A7791 SoC;
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H A Dhisilicon,kirin-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin SoCs PCIe host DT description
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
14 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15 It shares common functions with the PCIe DesignWare core driver and
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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H A Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
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H A Dfsl,imx6q-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
20 maxItems: 4
22 clock-names:
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H A Duniphier-pcie.txt1 Socionext UniPhier PCIe host controller bindings
3 This describes the devicetree bindings for PCIe host controller implemented
6 UniPhier PCIe host controller is based on the Synopsys DesignWare PCI core.
7 It shares common functions with the PCIe DesignWare core driver and inherits
9 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
12 - compatible: Should be "socionext,uniphier-pcie".
13 - reg: Specifies offset and length of the register set for the device.
14 According to the reg-names, appropriate register sets are required.
15 - reg-names: Must include the following entries:
16 "dbi" - controller configuration registers
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H A Dsocionext,uniphier-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe host controller
10 UniPhier PCIe host controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie.yaml#
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H A Dkirin-pcie.txt1 HiSilicon Kirin SoCs PCIe host DT description
3 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
4 It shares common functions with the PCIe DesignWare core driver and
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible:
12 "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
13 - reg: Should contain rc_dbi, apb, phy, config registers location and length.
14 - reg-names: Must include the following entries:
18 "config": PCIe configuration space registers.
19 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
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H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
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H A Dqcom,pcie-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm SC8280XP SoC PCIe root complex controller is based on the Synopsys
15 DesignWare PCIe IP.
20 - qcom,pcie-sa8540p
21 - qcom,pcie-sc8280xp
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
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H A Drockchip-pcie-host.txt1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: Must include the following names
11 - "axi-base"
12 - "apb-base"
13 - clocks: Must contain an entry for each entry in clock-names.
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H A Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCIe RC controller on Intel Gateway SoCs
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
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H A Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
15 ports (e.g. PCIe) and the lanes.
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
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H A Dqcom,qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
21 - qcom,ipq8074-qmp-pcie-phy
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/freebsd/share/man/man4/
H A Dmpi3mr.44 .\" SPDX-License-Identifier: BSD-2-Clause
13 .Nd "Broadcom MPIMR 3.0 IT/IR 24Gb/s SAS Tri-Mode RAID PCIe 4.0 driver"
17 .\" .Bd -ragged -offset indent
25 .Bd -literal -offset indent
31 driver provides support for Broadcom Ltd. MPIMR 3.0 IT/IR PCIe 4 controller.
37 .Bl -bullet -compact
39 Broadcom Ltd. SAS 4116 Tri-Mode RAID Adapter
41 Broadcom Ltd. 9670W-16i 24G PCIe 4.0 Tri-Mode RAID Adapters
43 Broadcom Ltd. 9670-24i 24G PCIe 4.0 Tri-Mode RAID Adapters
45 Broadcom Ltd. 9660-16i 24G PCIe 4.0 Tri-Mode RAID Adapters
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmvebu-gated-clock.txt12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
17 4 ge0 Gigabit Ethernet 0
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
29 -----------------------------------
32 4 ptp PTP
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
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/freebsd/lib/libpmc/pmu-events/arch/x86/cascadelakex/
H A Duncore-other.json10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
20 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
164 "ScaleUnit": "7.11E-06Bytes",
174 "ScaleUnit": "7.11E-06Bytes",
186 "ScaleUnit": "4Bytes",
198 "ScaleUnit": "4Bytes",
210 "ScaleUnit": "4Bytes",
222 "ScaleUnit": "4Bytes",
237 "ScaleUnit": "4Bytes",
252 "ScaleUnit": "4Bytes",
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/freebsd/lib/libpmc/pmu-events/arch/x86/skylakex/
H A Duncore-other.json10 …"BriefDescription": "LLC misses - Uncacheable reads (from cpu) . Derived from unc_cha_tor_inserts.…
20 "BriefDescription": "LLC misses - Uncacheable reads (from cpu) ",
164 "ScaleUnit": "7.11E-06Bytes",
174 "ScaleUnit": "7.11E-06Bytes",
186 "ScaleUnit": "4Bytes",
198 "ScaleUnit": "4Bytes",
210 "ScaleUnit": "4Bytes",
222 "ScaleUnit": "4Bytes",
237 "ScaleUnit": "4Bytes",
252 "ScaleUnit": "4Bytes",
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
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H A Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j784s4-evm-pcie0-pcie1-ep.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/ti,sci_pm_domain.h>
17 #include "k3-pinctrl.h"
32 #address-cells = <2>;
33 #size-cells = <2>;
34 interrupt-parent = <&gic500>;
36 pcie0_ep: pcie-ep@2900000 {
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