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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-keystone.txt3 Keystone PCI host Controller is based on the Synopsys DesignWare PCI
6 Documentation/devicetree/bindings/pci/designware-pcie.txt
8 Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
12 Required Properties:-
14 compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
15 Should be "ti,am654-pcie-rc" for RC on AM654x SoC
16 reg: Three register ranges as listed in the reg-names property
17 reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
22 interrupt-cells: should be set to 1
23 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
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H A Dsocionext,uniphier-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-pcie-ep
22 - socionext,uniphier-nx1-pcie-ep
28 reg-names:
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H A Dti,am65-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: TI AM65 PCI Endpoint
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: pci-ep.yaml#
19 - ti,am654-pcie-ep
24 reg-names:
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H A Dti-pci.txt1 TI PCI Controllers
4 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
5 Should be "ti,dra7-pcie-ep" for EP (deprecated)
6 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
7 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
8 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
9 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
10 - phys : list of PHY specifiers (used by generic PHY framework)
11 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
13 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
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H A Dti,j721e-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
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H A Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33 entry for each entry in the interrupt-names property.
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H A Dfsl,imx6q-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
15 thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
22 - fsl,imx8mm-pcie-ep
23 - fsl,imx8mq-pcie-ep
24 - fsl,imx8mp-pcie-ep
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H A Ddesignware-pcie.txt4 - compatible:
5 "snps,dw-pcie" for RC mode;
6 "snps,dw-pcie-ep" for EP mode;
7 - reg: For designware cores version < 4.80 contains the configuration
10 - reg-names: Must be "config" for the PCIe configuration space and "atu" for
15 - #address-cells: set to <3>
16 - #size-cells: set to <2>
17 - device_type: set to "pci"
18 - ranges: ranges for the PCI memory and I/O regions
19 - #interrupt-cells: set to <1>
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H A Drockchip,rk3399-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
13 - $ref: /schemas/pci/pci-ep.yaml#
14 - $ref: rockchip,rk3399-pcie-common.yaml#
18 const: rockchip,rk3399-pcie-ep
22 reg-names:
24 - const: apb-base
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H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep
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H A Drcar-pci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
4 ---
5 $id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car PCIe Endpoint
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
12 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
17 - enum:
18 - renesas,r8a774a1-pcie-ep # RZ/G2M
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H A Dpci-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/pci-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PCI Endpoint Controller
10 Common properties for PCI Endpoint Controller Nodes.
13 - Kishon Vijay Abraham I <kishon@ti.com>
17 pattern: "^pcie-ep@"
19 max-functions:
26 max-virtual-functions:
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H A Dfsl,imx6q-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
22 clock-names:
26 num-lanes:
29 fsl,imx7d-pcie-phy:
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H A Dqcom,pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qco
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H A Dfsl,imx6q-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
19 See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
25 - fsl,imx6q-pcie
26 - fsl,imx6sx-pcie
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H A Dcdns-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/cdns-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tom Joseph <tjoseph@cadence.com>
13 - $ref: cdns-pcie.yaml#
14 - $ref: pci-ep.yaml#
17 cdns,max-outbound-regions:
H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
23 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
29 - nvidia,tegra194-pcie-ep
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/freebsd/sys/contrib/openzfs/lib/libzutil/os/linux/
H A Dzutil_device_path_os.c9 * or https://opensource.org/licenses/CDDL-1.0.
54 return (-1); in zfs_append_partition()
56 (void) strcat(path, "-part1"); in zfs_append_partition()
60 return (-1); in zfs_append_partition()
62 if (isdigit(path[len-1])) { in zfs_append_partition()
76 * forms: "-partX", "pX", or "X", where X is a string of digits. The second
79 * expression "^([hsv]|xv)d[a-z]+", i.e. a scsi, ide, virtio or xen disk.
91 if ((part = strstr(tmp, "-part")) && part != tmp) { in zfs_strip_partition()
94 part > tmp + 1 && isdigit(*(part-1))) { in zfs_strip_partition()
188 if (buf[len - 1] == '\n') { in zfs_read_sysfs_file()
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dsam440ep.dts16 /dts-v1/;
19 #address-cells = <2>;
20 #size-cells = <1>;
34 #address-cells = <1>;
35 #size-cells = <0>;
39 model = "PowerPC,440EP";
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
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H A Dbamboo.dts14 /dts-v1/;
17 #address-cells = <2>;
18 #size-cells = <1>;
21 dcr-parent = <&{/cpus/cpu@0}>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 model = "PowerPC,440EP";
40 clock-frequency = <0>; /* Filled in by zImage */
41 timebase-frequency = <0>; /* Filled in by zImage */
42 i-cache-line-size = <32>;
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H A Dyosemite.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 model = "PowerPC,440EP";
38 clock-frequency = <0>; /* Filled in by zImage */
39 timebase-frequency = <0>; /* Filled in by zImage */
40 i-cache-line-size = <32>;
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H A Dhotfoot.dts4 * Copyright 2009 AbsoluteValue Systems <solomon@linux-wlan.com>
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 model = "PowerPC,405EP";
35 clock-frequency = <0>; /* Filled in by zImage */
36 timebase-frequency = <0>; /* Filled in by zImage */
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/freebsd/sys/dev/nvme/
H A Dnvme_pci.c1 /*-
2 * Copyright (C) 2012-2016 Intel Corporation
36 #include <dev/pci/pcireg.h>
37 #include <dev/pci/pcivar.h>
66 DRIVER_MODULE(nvme, pci, nvme_pci_driver, NULL, NULL);
81 { 0x09538086, 1, 0x3704, "DC P3500 SSD [Add-in Card]" },
83 { 0x09538086, 1, 0x3709, "DC P3600 SSD [Add-in Card]" },
100 nvme_match(uint32_t devid, uint16_t subdevice, struct _pcsid *ep) in nvme_match() argument
102 if (devid != ep->devid) in nvme_match()
105 if (!ep->match_subdevice) in nvme_match()
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/freebsd/share/man/man4/
H A Dral.41 .\"-
2 .\" SPDX-License-Identifier: ISC
4 .\" Copyright (c) 2005-2010 Damien Bergamini <damien.bergamini@free.fr>
28 .Bd -ragged -offset indent
39 .Bd -literal -offset indent
45 driver supports PCI/PCIe/CardBus wireless adapters based on the Ralink RT2500,
62 This chipset uses the MIMO (multiple-input multiple-output) technology with
67 The RT2700 chipset is a low-cost version of the RT2800 chipset.
80 The RT3090 chipset is the first generation of single-chip 802.11n adapters
108 The RT3900E chipset is a single-chip 802.11n adapters from Ralink.
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/freebsd/usr.sbin/pciconf/
H A Dpciconf.c38 #include <dev/pci/pcireg.h>
93 "usage: pciconf -l [-BbcevV] [device]\n" in usage()
94 " pciconf -a device\n" in usage()
95 " pciconf -r [-b | -h] device addr[:addr2]\n" in usage()
96 " pciconf -w [-b | -h] device addr value\n" in usage()
97 " pciconf -D [-b | -h | -x] device bar [start [count]]" in usage()
113 while ((c = getopt(argc, argv, "aBbcDehlrwVv")) != -1) { in main()
236 if (ioctl(fd, PCIOCGETCONF, &pc) == -1) in list_devs()
248 warnx("PCI device list changed, please try again"); in list_devs()
263 printf("%s%d@pci%d:%d:%d:%d:" in list_devs()
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