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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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/linux/Documentation/fpga/
H A Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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/linux/include/linux/firmware/intel/
H A Dstratix10-svc-client.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
12 * fpga: for FPGA configuration
15 #define SVC_CLIENT_FPGA "fpga"
34 * FPGA configuration, FPGA should be in user mode.
59 * Set to FPGA configuration type (full or partial).
65 * timeout value used in Stratix10 FPGA manager driver.
77 * enum stratix10_svc_command_code - supported service commands
79 * @COMMAND_NOOP: do 'dummy' request for integration/debug/trouble-shooting
81 * @COMMAND_RECONFIG: ask for FPGA configuration preparation, return status
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/linux/drivers/fpga/
H A Dsocfpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Altera SOCFPGA
5 * Copyright (C) 2013-2015 Altera Corporation
9 #include <linux/fpga/fpga-mgr.h>
96 /* In power-up order. Reverse for power-down. */
98 "FPGA-1.5V",
99 "FPGA-1.1V",
100 "FPGA-2.5V",
136 return readl(priv->fpga_base_addr + reg_offset); in socfpga_fpga_readl()
142 writel(value, priv->fpga_base_addr + reg_offset); in socfpga_fpga_writel()
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/linux/include/linux/firmware/
H A Dxlnx-zynqmp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2014-2021 Xilinx
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
108 * Firmware FPGA Manager flags
109 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
110 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
115 /* FPGA Status Reg */
145 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error.
203 /* PMU-FW return status codes */
524 * enum pm_sd_config_type - PM SD configuration.
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
58 /* Emulation on FPGA, in "Maximus" System.
60 * (access to non-DC registers will hang FPGA) */
62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
237 Must be zero for wired displays and non-zero for
330 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
402 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
408 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
29 * we shouldn't touch PCIe config. */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
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