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/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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/linux/Documentation/fpga/
H A Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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/linux/include/linux/firmware/intel/
H A Dstratix10-svc-client.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
12 * fpga: for FPGA configuration
15 #define SVC_CLIENT_FPGA "fpga"
34 * FPGA configuration, FPGA should be in user mode.
59 * Set to FPGA configuration type (full or partial).
65 * timeout value used in Stratix10 FPGA manager driver.
77 * enum stratix10_svc_command_code - supported service commands
79 * @COMMAND_NOOP: do 'dummy' request for integration/debug/trouble-shooting
81 * @COMMAND_RECONFIG: ask for FPGA configuration preparation, return status
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/linux/drivers/fpga/
H A Dsocfpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Altera SOCFPGA
5 * Copyright (C) 2013-2015 Altera Corporation
9 #include <linux/fpga/fpga-mgr.h>
96 /* In power-up order. Reverse for power-down. */
98 "FPGA-1.5V",
99 "FPGA-1.1V",
100 "FPGA-2.5V",
136 return readl(priv->fpga_base_addr + reg_offset); in socfpga_fpga_readl()
142 writel(value, priv->fpga_base_addr + reg_offset); in socfpga_fpga_writel()
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/linux/include/linux/firmware/
H A Dxlnx-zynqmp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2014-2021 Xilinx
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
108 * Firmware FPGA Manager flags
109 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
110 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
115 /* FPGA Status Reg */
145 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error.
203 /* PMU-FW return status codes */
524 * enum pm_sd_config_type - PM SD configuration.
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/linux/drivers/firmware/xilinx/
H A Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
28 #include <linux/firmware/xlnx-zynqmp.h>
29 #include <linux/firmware/xlnx-event-manager.h>
30 #include "zynqmp-debug.h"
37 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
39 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
54 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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/linux/drivers/firmware/
H A Dstratix10-svc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation
19 #include <linux/firmware/intel/stratix10-smc.h>
20 #include <linux/firmware/intel/stratix10-svc-client.h>
24 * SVC_NUM_DATA_IN_FIFO - number of struct stratix10_svc_data in the FIFO
26 * SVC_NUM_CHANNEL - number of channel supported by service layer driver
28 * FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS - claim back the submitted buffer(s)
29 * from the secure world for FPGA manager to reuse, or to free the buffer(s)
30 * when all bit-stream data had be send.
32 * FPGA_CONFIG_STATUS_TIMEOUT_SEC - poll the FPGA configuration status,
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
29 * we shouldn't touch PCIe config. */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
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/linux/drivers/infiniband/hw/hfi1/
H A Dchip.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
32 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
78 #define SEC_SC_HALTED 0x4 /* per-context only */
79 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
87 * 0 - User Fecn Handling
88 * 1 - Vnic
89 * 2 - AIP
90 * 3 - Verbs
101 #define emulator_rev(dd) ((dd)->irev >> 8)
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