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/freebsd/sys/dev/clk/
H A Dclk.c1 /*-
49 #include <dev/clk/clk.h>
57 struct clk;
65 static int clknode_method_init(struct clknode *clk, device_t dev);
66 static int clknode_method_recalc_freq(struct clknode *clk, uint64_t *freq);
67 static int clknode_method_set_freq(struct clknode *clk, uint64_t fin,
69 static int clknode_method_set_gate(struct clknode *clk, bool enable);
70 static int clknode_method_set_mux(struct clknode *clk, int idx);
87 * Clock node - basic element for modeling SOC clock graph. It holds the clock
99 /* String based parent list. */
[all …]
H A Dclk_fixed.c1 /*-
47 #include <dev/clk/clk_fixed.h>
52 static int clknode_fixed_init(struct clknode *clk, device_t dev);
53 static int clknode_fixed_recalc(struct clknode *clk, uint64_t *freq);
54 static int clknode_fixed_set_freq(struct clknode *clk, uint64_t fin,
75 clknode_fixed_init(struct clknode *clk, device_t dev) in clknode_fixed_init() argument
79 sc = clknode_get_softc(clk); in clknode_fixed_init()
80 if (sc->freq == 0) in clknode_fixed_init()
81 clknode_init_parent_idx(clk, 0); in clknode_fixed_init()
86 clknode_fixed_recalc(struct clknode *clk, uint64_t *freq) in clknode_fixed_recalc() argument
[all …]
/freebsd/sys/arm/ti/clk/
H A Dclock_common.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_mux.h>
54 read_clock_cells(device_t dev, struct clock_cell_info *clk) { in read_clock_cells() argument
56 phandle_t node, parent, *cells; in read_clock_cells() local
61 /* Get names of parent clocks */ in read_clock_cells()
63 clk->num_clock_cells = numbytes_clocks / sizeof(cell_t); in read_clock_cells()
69 clk->clock_cells = malloc(numbytes_clocks, M_DEVBUF, M_WAITOK|M_ZERO); in read_clock_cells()
70 clk->clock_cells_ncells = malloc(clk->num_clock_cells*sizeof(uint8_t), in read_clock_cells()
72 OF_getencprop(node, "clocks", clk->clock_cells, numbytes_clocks); in read_clock_cells()
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/freebsd/sys/dev/qcom_clk/
H A Dqcom_clk_rcg2.c1 /*-
34 #include <dev/clk/clk.h>
35 #include <dev/clk/clk_div.h>
36 #include <dev/clk/clk_fixed.h>
37 #include <dev/clk/clk_mux.h>
52 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_CFG_REG)
54 ((sc)->cmd_rcgr + QCOM_CLK_RCG2_CMD_REG)
56 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_M_REG)
58 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_N_REG)
60 ((sc)->cmd_rcgr + (sc)->cfg_offset + QCOM_CLK_RCG2_D_REG)
[all …]
H A Dqcom_clk_apssdiv.c1 /*-
34 #include <dev/clk/clk.h>
35 #include <dev/clk/clk_div.h>
36 #include <dev/clk/clk_fixed.h>
37 #include <dev/clk/clk_mux.h>
66 qcom_clk_apssdiv_calc_rate(struct clknode *clk, uint64_t freq, uint32_t cdiv) in qcom_clk_apssdiv_calc_rate() argument
71 * The divisor isn't a linear map with a linear pre-divisor. in qcom_clk_apssdiv_calc_rate()
85 qcom_clk_apssdiv_recalc(struct clknode *clk, uint64_t *freq) in qcom_clk_apssdiv_recalc() argument
90 sc = clknode_get_softc(clk); in qcom_clk_apssdiv_recalc()
97 CLKDEV_DEVICE_LOCK(clknode_get_device(sc->clknode)); in qcom_clk_apssdiv_recalc()
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/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc32xx.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 #include <dt-bindings/clock/lpc32xx-clock.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 interrupt-parent = <&mic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "arm,arm926ej-s";
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/freebsd/sys/dev/clk/xilinx/
H A Dzynqmp_clock.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
44 #include <dev/clk/clk.h>
45 #include <dev/clk/clk_fixed.h>
47 #include <dev/clk/xilinx/zynqmp_clk_mux.h>
48 #include <dev/clk/xilinx/zynqmp_clk_pll.h>
49 #include <dev/clk/xilinx/zynqmp_clk_fixed.h>
50 #include <dev/clk/xilinx/zynqmp_clk_div.h>
51 #include <dev/clk/xilinx/zynqmp_clk_gate.h>
85 #define CLK_ID_TO_ZYNQMP(x) ((x) - 1)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-mt65xx.txt4 - compatible: should be one of the following.
5 - mediatek,mt2701-spi: for mt2701 platforms
6 - mediatek,mt2712-spi: for mt2712 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms
8 - mediatek,mt6765-spi: for mt6765 platforms
9 - mediatek,mt7622-spi: for mt7622 platforms
10 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
11 - mediatek,mt8135-spi: for mt8135 platforms
12 - mediatek,mt8173-spi: for mt8173 platforms
13 - mediatek,mt8183-spi: for mt8183 platforms
[all …]
H A Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
[all …]
/freebsd/sys/dev/clk/rockchip/
H A Drk_clk_armclk.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/clk/clk.h>
34 #include <dev/clk/rockchip/rk_clk_armclk.h>
73 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
79 rk_clk_armclk_init(struct clknode *clk, device_t dev) in rk_clk_armclk_init() argument
84 sc = clknode_get_softc(clk); in rk_clk_armclk_init()
87 DEVICE_LOCK(clk); in rk_clk_armclk_init()
88 READ4(clk, sc->muxdiv_offset, &val); in rk_clk_armclk_init()
89 DEVICE_UNLOCK(clk); in rk_clk_armclk_init()
[all …]
H A Drk_clk_mux.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #include <dev/clk/clk.h>
40 #include <dev/clk/rockchip/rk_cru.h>
41 #include <dev/clk/rockchip/rk_clk_mux.h>
59 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
64 static int rk_clk_mux_init(struct clknode *clk, device_t dev);
65 static int rk_clk_mux_set_mux(struct clknode *clk, int idx);
66 static int rk_clk_mux_set_freq(struct clknode *clk, uint64_t fparent,
88 rk_clk_mux_get_grf(struct clknode *clk) in rk_clk_mux_get_grf() argument
[all …]
H A Drk_clk_composite.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/clk/clk.h>
35 #include <dev/clk/rockchip/rk_clk_composite.h>
68 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
74 rk_clk_composite_read_4(struct clknode *clk, bus_addr_t addr, uint32_t *val) in rk_clk_composite_read_4() argument
78 sc = clknode_get_softc(clk); in rk_clk_composite_read_4()
79 if (sc->grf) in rk_clk_composite_read_4()
80 *val = SYSCON_READ_4(sc->grf, addr); in rk_clk_composite_read_4()
82 CLKDEV_READ_4(clknode_get_device(clk), addr, val); in rk_clk_composite_read_4()
[all …]
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k0500.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
23 clocks = <&clk LOONGSON2_NODE_CLK>;
27 ref_100m: clock-ref-100m {
[all …]
H A Dloongson-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
24 clocks = <&clk LOONGSON2_NODE_CLK>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-cp11x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
9 #include <dt-bindings/thermal/thermal.h>
11 #include "armada-common.dtsi"
27 thermal-zones {
28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) {
29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
42 cooling-maps { };
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nuvoton/
H A Dnuvoton-common-npcm8xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-binding
57 clk: clock-controller@f0801000 { global() label
[all...]
/freebsd/sys/arm64/freescale/imx/clk/
H A Dimx_clk_composite.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/clk/clk.h>
34 #include <arm64/freescale/imx/clk/imx_clk_composite.h>
42 #define TARGET_ROOT_PRE_PODF(n) ((((n) - 1) & 0x7) << 16)
46 #define TARGET_ROOT_POST_PODF(n) ((((n) - 1) & 0x3f) << 0)
69 printf("%s:(%s)" format, __func__, clknode_get_name(clk), arg)
75 imx_clk_composite_init(struct clknode *clk, device_t dev) in imx_clk_composite_init() argument
80 sc = clknode_get_softc(clk); in imx_clk_composite_init()
82 DEVICE_LOCK(clk); in imx_clk_composite_init()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7981b.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 #include <dt-bindings/clock/mediatek,mt7981-clk.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/reset/mt7986-resets.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
18 compatible = "arm,cortex-a53";
[all …]
/freebsd/sys/arm/freescale/vybrid/
H A Dvf_ccm.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2013-2014 Ruslan Bukin <br@bsdpad.com>
153 struct clk { struct
165 static struct clk ipg_clk = { argument
189 static struct clk pll4_clk = {
201 static struct clk sai3_clk = {
213 static struct clk cko1_clk = {
225 static struct clk esdhc0_clk = {
237 static struct clk esdhc1_clk = {
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/st/
H A Dst,flexgen.txt5 - a clock cross bar (represented by a mux element)
6 - a pre and final dividers (represented by a divider and gate elements)
13 -------------------------------------------------------------------
15 | --------------------------------------------- |
16 | | ------- -------- -------- | |
18 ---|-----------------|-->| | | | | | | |
20 | | ------- | | | |Pre | |Final | | |
22 | |->| | | | | | x32 | | x32 | | |
23 | | | odf_0|----|-->| | | | | | | |
28 | | ------- | | | | | | | | |
[all …]
/freebsd/sys/dev/clk/allwinner/
H A Daw_clk_m.c1 /*-
30 #include <dev/clk/clk.h>
32 #include <dev/clk/allwinner/aw_clk.h>
33 #include <dev/clk/allwinner/aw_clk_m.h>
40 * clk = clkin / m
42 * 1) Set the parent freq
43 * 2) Support Setting the parent to a multiple
69 aw_clk_m_init(struct clknode *clk, device_t dev) in aw_clk_m_init() argument
74 sc = clknode_get_softc(clk); in aw_clk_m_init()
77 if ((sc->flags & AW_CLK_HAS_MUX) != 0) { in aw_clk_m_init()
[all …]
H A Dccu_h6.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
41 #include <dev/clk/clk_div.h>
42 #include <dev/clk/clk_fixed.h>
43 #include <dev/clk/clk_mux.h>
45 #include <dev/clk/allwinner/aw_ccung.h>
47 #include <dt-bindings/clock/sun50i-h6-ccu.h>
48 #include <dt-bindings/reset/sun50i-h6-ccu.h>
50 /* Non-exported clocks */
117 CCU_GATE(CLK_BUS_PSI, "bus-psi", "psi_ahb1_ahb2", 0x79c, 0)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cell
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/zte/
H A Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
[all …]

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