parallel\-memories (full) in projects: linux

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Searched +full:parallel +full:- +full:memories (Results 1 – 15 of 15) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/spi/
H A D	spi-peripheral-props.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Peripheral-specific properties for a SPI bus. 11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be 13 need to be defined in the peripheral node because they are per-peripheral and 19 - Mark Brown <broonie@kernel.org> 27 - minimum: 0 32 spi-cs-high: [all …]`
/freebsd/contrib/one-true-awk/testdir/
H A D	funstack.in	`2 %%% BibTeX-file{ 23 %%% (incompletely) 1970 -- 1979. 50 %%% covering 1958--1996 became too large (about 65 %%% Algorithms 1--492. For Algorithms 493--686, 72 %%% cross-referenced in both directions, so 75 %%% Corrigenda. Cross-referenced entries are 77 %%% that each is completely self-contained. 83 %%% ftp://netlib.bell-labs.com/netlib/toms. 88 %%% http://ciir.cs.umass.edu/cgi-bin/web_query_form/public/cacm2.1. 90 %%% The initial draft of entries for 1981 -- [all …]`
H A D	funstack.ok	23 for Pert Networks . . . . . . . . . . . 738--739 29 the First Kind . . . . . . . . . . . . . 479--480 40 for Arguments Larger than One . . . . . 488--492 52 M. C. Pike ACM Algorithm 299: Chi-Squared Integral 243--244 57 Edsger Wybe Dijkstra Go to statement considered harmful . . . 147--148 62 ANSI Subcommittee X3J3 Clarification of Fortran Standards --- 63 Initial Progress . . . . . . . . . . . . 289--294 69 Computer Organization . . . . . . . . . 489--498 74 V. Y. Lum Multi-Attribute Retrieval with Combined 75 Indexes . . . . . . . . . . . . . . . . 660--665 [all …]
/freebsd/sys/dev/aac/
H A D	aacreg.h	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 5 * Copyright (c) 2000-2001 Scott Long 48 * Where datastructure layouts are closely parallel to the Adaptec sample code, 49 * retain their naming conventions (for now) to aid in cross-referencing. 54 * be 16-byte aligned, and are sized as follows: 56 #define AAC_HOST_NORM_CMD_ENTRIES 8 /* command adapter->host, 58 #define AAC_HOST_HIGH_CMD_ENTRIES 4 /* command adapter->host, 60 #define AAC_ADAP_NORM_CMD_ENTRIES 512 /* command host->adapter, 62 #define AAC_ADAP_HIGH_CMD_ENTRIES 4 /* command host->adapter, [all …]
/freebsd/sys/dev/aacraid/
H A D	aacraid_reg.h	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 5 * Copyright (c) 2000-2001 Scott Long 7 * Copyright (c) 2001-2010 Adaptec, Inc. 8 * Copyright (c) 2010-2012 PMC-Sierra, Inc. 49 * Where datastructure layouts are closely parallel to the Adaptec sample code, 50 * retain their naming conventions (for now) to aid in cross-referencing. 62 * List structure used to chain FIBs (used by the adapter - we hang FIBs off 92 #define AAC_FIB_DATASIZE (512 - sizeof(struct aac_fib_header)) 286 CT_RAID5D, /* raid5 distributed hot-sparing */ [all …]
/illumos-gate/usr/src/lib/libfru/libfrureg/
H A D	frudefs.c	`28 * This file is AUTO-generated DO NOT EDIT 82 { 0x54, "Hewlett-Packard" }, 108 { 0x8c, "Monolithic Memories" }, 154 { 0xe6, "PMC-Sierra" }, 164 { 0xfb, "Allied-Signal" }, 183 { 0x11f, "Integ. Memories Tech." }, 189 { 0x12a, "Hagiwara Sys-Com" }, 276 { 0x1da, "Dane-Elec" }, 306 { 0x216, "C-Port Corporation" }, 338 { 0x257, "Com-Tier" }, [all …]`
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A D	reg_addr_ah_compile15.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 87 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 96 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 98 … has_mem_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 144 …_SYS_ERR (0x1<<30) // Fatal or Non-Fatal Error Message s… 148 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… 149 …:0x20 This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)… [all …]
H A D	reg_addr_bb.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_k2.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr_e5.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 84 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 85 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 86 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 87 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 89 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 91 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 99 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
H A D	reg_addr.h	9 * or http://opensource.org/licenses/CDDL-1.0. 23 * Copyright 2014-2017 Cavium, Inc. 30 * at http://opensource.org/licenses/CDDL-1.0 85 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 86 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 87 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 88 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 90 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 92 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 100 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A D	reg_addr.h	2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 116 … (0x1<<9) // Fast back-to-back transaction ena… 128 … (0x1<<23) // Fast back-to-back capable. Not ap… 145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]
/freebsd/sys/dev/bxe/
H A D	bxe.c	1 /- 2 SPDX-License-Identifier: BSD-2-Clause 4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 64 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per 241 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 / 253 / Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) / 256 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode"); 261 &bxe_queue_count, 0, "Multi-Queue queue count"); 288 / PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */ 289 static int bxe_mrrs = -1; [all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D	57712_reg.h	3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32 9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 14 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 15 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 16 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… 17 …set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc… [all …]
/freebsd/contrib/ncurses/misc/
H A D	terminfo.src	7 # bug-ncurses@gnu.org 19 # under the ncurses MIT-style license. That was the effect of the agreement 33 # some portions of the data are derivative work under a compatible MIT-style 36 #------------------------------------------------------------------------------ 37 # https://invisible-island.net/ncurses/ncurses.faq.html#terminfo_copying 38 # https://invisible-island.net/personal/copyrights.html#removing_notes 39 #------------------------------------------------------------------------------ 48 # Please e-mail changes to terminfo@thyrsus.com; the old termcap@berkeley.edu 54 # This file describes the capabilities of various character-cell terminals, 55 # as needed by software such as screen-oriented editors. [all …]