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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cs-high, etc. or they could
14 per-peripheral and there can be multiple peripherals attached to a
20 - Mark Brown <broonie@kernel.org>
28 - minimum: 0
33 spi-cs-high:
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/linux/Documentation/admin-guide/mm/
H A Duserfaultfd.rst8 Userfaults allow the implementation of on-demand paging from userland
38 Vmas are not suitable for page- (or hugepage) granular fault tracking
48 is a corner case that would currently return ``-EBUSY``).
54 ----------------------
63 - Any user can always create a userfaultfd which traps userspace page faults
67 - In order to also trap kernel page faults for the address space, either the
84 --------------------------
101 - The ``UFFD_FEATURE_EVENT_*`` flags indicate that various other events
103 detail below in the `Non-cooperative userfaultfd`_ section.
105 - ``UFFD_FEATURE_MISSING_HUGETLBFS`` and ``UFFD_FEATURE_MISSING_SHMEM``
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/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-zc770-xm013.dts1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include "zynq-7000.dtsi"
12 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
24 stdout-path = "serial0:115200n8";
39 phy-mode = "rgmii-id";
40 phy-handle = <&ethernet_phy>;
42 ethernet_phy: ethernet-phy@7 {
49 clock-frequency = <400000>;
51 si570: clock-generator@55 {
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H A Dzynq-zc706.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
6 /dts-v1/;
7 #include "zynq-7000.dtsi"
11 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
30 stdout-path = "serial0:115200n8";
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
40 ps-clk-frequency = <33333333>;
45 phy-mode = "rgmii-id";
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/linux/arch/sh/kernel/cpu/sh4a/
H A Dperf_event.c1 // SPDX-License-Identifier: GPL-2.0
3 * Performance events support for SH-4A performance counters
24 * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR
28 * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and
59 * ---------- -----------
65 * 0x0203 instruction execution in parallel
72 * 0x0028 number of accesses to instruction memories
76 * 0x0030 number of reads to operand memories
77 * 0x0038 number of writes to operand memories
102 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0029, /* I-cache */
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/linux/Documentation/driver-api/
H A Dedac.rst5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
19 output 4 and 8 bits each (x4, x8). Grouping several of these in parallel
26 parallel. In general, this is the Field Replaceable Unit (FRU) which
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
56 one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
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/linux/sound/drivers/
H A Dmtpav.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * -----
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/linux/Documentation/block/
H A Dblk-mq.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Multi-Queue Block IO Queueing Mechanism (blk-mq)
7 The Multi-Queue Block IO Queueing Mechanism is an API to enable fast storage
16 ----------
26 However, with the development of Solid State Drives and Non-Volatile Memories
28 high parallel access, the bottleneck of the stack had moved from the storage
30 in those devices' design, the multi-queue mechanism was introduced.
36 to different CPUs) wanted to perform block IO. Instead of this, the blk-mq API
42 ---------
45 for instance), blk-mq takes action: it will store and manage IO requests to
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/linux/drivers/bus/
H A Dqcom-ebi2.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * an older version of the Qualcomm Parallel Interface Controller (QPIC)
41 * Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
42 * memory continues to drive the data bus after OE is de-asserted.
45 * Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
49 * Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
51 * Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
53 * Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
55 * Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
74 * Bits 31-28: ?
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/linux/include/linux/spi/
H A Dspi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later
38 * INTERFACES between SPI controller-side drivers and SPI target protocol handlers,
44 * struct spi_statistics - statistics for spi transfers
45 * @syncp: seqcount to protect members in this struct for per-cpu update
46 * on 32-bit systems
48 * @messages: number of spi-message
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/linux/arch/m68k/kernel/
H A Dhead.S1 /* SPDX-License-Identifier: GPL-2.0-or-later
2 ** -*- mode: asm -*-
4 ** head.S -- This file contains the initial boot code for the
20 ** ++ Bjoern & Roman: ATARI-68040 support for the Medusa
23 ** Magnum- and FX-alternate ram
26 ** for linux-2.1.115
45 * . Enable cache memories
49 * 1) Remove register dependency through-out the file.
57 * write-ups on the structure of the file, and the features of the
61 * ------------------
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_main.c3 * Copyright (c) 2007-2013 Broadcom Corporation
36 #include <linux/dma-mapping.h>
83 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
84 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
85 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
86 #define FW_FILE_NAME_E1_V15 "bnx2x/bnx2x-e1-" FW_FILE_VERSION_V15 ".fw"
87 #define FW_FILE_NAME_E1H_V15 "bnx2x/bnx2x-e1h-" FW_FILE_VERSION_V15 ".fw"
88 #define FW_FILE_NAME_E2_V15 "bnx2x/bnx2x-e2-" FW_FILE_VERSION_V15 ".fw"
117 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
124 static int mrrs = -1;
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/linux/drivers/infiniband/hw/hfi1/
H A Dchip.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
32 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
78 #define SEC_SC_HALTED 0x4 /* per-context only */
79 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
87 * 0 - User Fecn Handling
88 * 1 - Vnic
89 * 2 - AIP
90 * 3 - Verbs
101 #define emulator_rev(dd) ((dd)->irev >> 8)
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