Home
last modified time | relevance | path

Searched +full:panel +full:- +full:dsi (Results 1 – 25 of 131) sorted by relevance

123456

/freebsd/sys/contrib/device-tree/Bindings/display/panel/
H A Dpanel-dsi-cm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/pane
[all...]
H A Dsharp,lq101r1sx01.txt1 Sharp Microelectronics 10.1" WQXGA TFT LCD panel
3 This panel requires a dual-channel DSI host to operate. It supports two modes:
4 - left-right: each channel drives the left or right half of the screen
5 - even-odd: each channel drives the even or odd lines of the screen
7 Each of the DSI channels controls a separate DSI peripheral. The peripheral
8 driven by the first link (DSI-LINK1), left or even, is considered the primary
10 to the peripheral driven by the second link (DSI-LINK2, right or odd).
12 Note that in video mode the DSI-LINK1 interface always provides the left/even
13 pixels and DSI-LINK2 always provides the right/odd pixels. In command mode it
19 - compatible: should be "sharp,lq101r1sx01"
[all …]
H A Dsharp,lq101r1sx01.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/sharp,lq101r1sx01.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sharp Microelectronics 10.1" WQXGA TFT LCD panel
10 - Thierry Reding <treding@nvidia.com>
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
14 - left-right: each channel drives the left or right half of the screen
15 - even-odd: each channel drives the even or odd lines of the screen
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
[all …]
H A Dpanel-simple-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/pane
[all...]
H A Dpanel-dsi-cm.txt1 Generic MIPI DSI Command Mode Panel
5 - compatible: "panel-dsi-cm"
8 - label: a symbolic name for the panel
9 - reset-gpios: panel reset gpio
10 - te-gpios: panel TE gpio
13 - Video port for DSI input
16 -------
19 compatible = "tpo,taal", "panel-dsi-cm";
22 reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>;
26 remote-endpoint = <&dsi1_out_ep>;
H A Dsamsung,s6d7aa0.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/samsung,s6d7aa0.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S6D7AA0 MIPI-DSI LCD panel controller
10 - Artur Weber <aweber.kernel@gmail.com>
13 - $ref: panel-common.yaml#
18 - enum:
19 # 1280x800 LSL080AL02 panel
20 - samsung,lsl080al02
[all …]
H A Dnovatek,nt36672a.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/panel/novatek,nt36672a.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Novatek NT36672A based DSI display Panels
10 - Sumit Semwal <sumit.semwal@linaro.org>
13 The nt36672a IC from Novatek is a generic DSI Panel IC used to drive dsi
15 Right now, support is added only for a Tianma FHD+ LCD display panel with a
16 resolution of 1080x2246. It is a video mode DSI panel.
19 - $ref: panel-common.yaml#
[all …]
H A Dorisetech,otm8009a.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/orisetec
[all...]
H A Debbg,ft8719.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/panel/ebbg,ft8719.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EBBG FT8719 MIPI-DSI LCD panel
10 - Joel Selvaraj <jo@jsfamily.in>
13 The FT8719 panel from EBBG is a FHD+ LCD display panel with a resolution
14 of 1080x2246. It is a video mode DSI panel. The backlight is managed
18 - $ref: panel-common.yaml#
26 description: DSI virtual channel of the peripheral
[all …]
H A Draydium,rm67191.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/raydium,rm67191.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Raydium RM67171 OLED LCD panel with MIPI-DSI protocol
10 - Robert Chiras <robert.chiras@nxp.com>
13 - $ref: panel-common.yaml#
21 reset-gpios: true
22 width-mm: true
23 height-mm: true
[all …]
H A Dsony,tulip-truly-nt35521.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/sony,tulip-truly-nt35521.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony Tulip Truly NT35521 5.24" 1280x720 MIPI-DSI Panel
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Sony Tulip Truly NT35521 is a 5.24" 1280x720 MIPI-DSI panel, which
14 can be found no Sony Xperia M4 phone. The panel backlight is managed
15 through DSI link.
18 - $ref: panel-common.yaml#
[all …]
H A Draydium,rm68200.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/raydiu
[all...]
H A Drocktech,jh057n00900.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/rocktec
[all...]
H A Draspberrypi,7inch-touchscreen.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/raspberrypi,7inch-touchscreen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eric Anholt <eric@anholt.net>
11 - Thierry Reding <thierry.reding@gmail.com>
14 This DSI panel contains:
16 - TC358762 DSI->DPI bridge
17 - Atmel microcontroller on I2C for power sequencing the DSI bridge and
19 - Touchscreen controller on I2C for touch input
[all …]
H A Dsony,td4353-jdi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/sony,td4353-jdi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sony TD4353 JDI 5 / 5.7" 2160x1080 MIPI-DSI Panel
10 - Konrad Dybcio <konrad.dybcio@somainline.org>
14 MIPI-DSI panel, used in Xperia XZ2 and XZ2 Compact smartphones.
17 - $ref: panel-common.yaml#
21 const: sony,td4353-jdi-tama
27 vddio-supply:
[all …]
H A Dboe,tv101wum-nl6.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/boe,tv101wum-nl6.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BOE TV101WUM-NL6 DSI Display Panel
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
14 - $ref: panel-common.yaml#
19 # BOE TV101WUM-NL6 10.1" WUXGA TFT LCD panel
20 - boe,tv101wum-nl6
[all …]
H A Dmantix,mlaf057we51-x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/manti
[all...]
H A Dsitronix,st7701.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/sitroni
[all...]
H A Dsamsung,amoled-mipi-dsi.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/samsung,amoled-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung AMOLED MIPI-DSI panels
10 - Hoegeun Kwon <hoegeun.kwon@samsung.com>
13 - $ref: panel-common.yaml#
15 - if:
20 - samsung,s6e3ha2
21 - samsung,s6e3hf2
[all …]
H A Dhimax,hx8394.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/hima
[all...]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Ddsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for DSI Display Panels
10 - Linus Walleij <linus.walleij@linaro.org>
13 This document defines device tree properties common to DSI, Display
18 When referenced from panel device tree bindings the properties defined in
19 this document are defined as follows. The panel device tree bindings are
22 Notice: this binding concerns DSI panels connected directly to a master
[all …]
H A Dbrcm,bcm-vc4.txt8 - compatible: Should be "brcm,bcm2835-vc4" or "brcm,cygnus-vc4"
11 - compatible: Should be one of "brcm,bcm2835-pixelvalve0",
12 "brcm,bcm2835-pixelvalve1", or "brcm,bcm2835-pixelvalve2"
13 - reg: Physical base address and length of the PV's registers
14 - interrupts: The interrupt number
15 See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
18 - compatible: Should be "brcm,bcm2835-hvs"
19 - reg: Physical base address and length of the HVS's registers
20 - interrupts: The interrupt number
21 See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddsi.txt1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dcdns,dsi.txt1 Cadence DSI bridge
4 The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
7 - compatible: should be set to "cdns,dsi".
8 - reg: physical base address and length of the controller's registers.
9 - interrupts: interrupt line connected to the DSI bridge.
10 - clocks: DSI bridge clocks.
11 - clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
12 - phys: phandle link to the MIPI D-PHY controller.
13 - phy-names: must contain "dphy".
14 - #address-cells: must be set to 1.
[all …]
H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358775 DSI to LVDS bridge
10 - Vinay Simha BN <simhavcs@gmail.com>
13 This binding supports DSI to LVDS bridge TC358775
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
20 panel, limited by 270 MHz LVDS speed.
[all …]

123456