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/linux/drivers/gpu/drm/xe/
H A Dxe_pt_walk.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * DOC: GPU page-table tree walking.
9 * The utilities in this file are similar to the CPU page-table walk
11 * the various levels of a page-table tree with an unsigned integer rather
12 * than by name. 0 is the lowest level, and page-tables with level 0 can
14 * can. The user of the utilities determines the highest level.
17 * Each struct xe_ptw, regardless of level is referred to as a page table, and
18 * multiple page tables typically form a page table tree with page tables at
19 * intermediate levels being page directories pointing at page tables at lower
20 * levels. A shared page table for a given address range is a page-table which
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H A Dxe_pt_walk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
12 * struct xe_ptw - base class for driver pagetable subclassing.
15 * Drivers could subclass this, and if it's a page-directory, typically
23 * struct xe_pt_walk - Embeddable struct for walk parameters
29 * @shifts: Array of page-table entry shifts used for the
30 * different levels, starting out with the leaf level 0
31 * page-shift as the first entry. It's legal for this pointer to be
35 /** @max_level: Highest populated level in @sizes */
47 * typedef xe_pt_entry_fn - gpu page-table-walk callback-function
48 * @parent: The parent page.table.
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_mmu.c1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
17 #include <linux/dma-mapping.h>
23 #define PVR_MASK_FROM_SIZE(size_) (~((size_) - U64_C(1)))
26 * The value of the device page size (%PVR_DEVICE_PAGE_SIZE) is currently
27 * pegged to the host page size (%PAGE_SIZE). This chunk of macro goodness both
28 * ensures that the selected host page size corresponds to a valid device page
56 # error Unsupported device page size PVR_DEVICE_PAGE_SIZE
61 (PVR_DEVICE_PAGE_SHIFT - PVR_SHIFT_FROM_SIZE(SZ_4K)))
64 PVR_MMU_SYNC_LEVEL_NONE = -1,
77 * pvr_mmu_set_flush_flags() - Set MMU cache flush flags for next call to
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/linux/arch/x86/kvm/mmu/
H A Dtdp_iter.c1 // SPDX-License-Identifier: GPL-2.0
9 * Recalculates the pointer to the SPTE for the current GFN and level and
14 iter->sptep = iter->pt_path[iter->level - 1] + in tdp_iter_refresh_sptep()
15 SPTE_INDEX(iter->gfn << PAGE_SHIFT, iter->level); in tdp_iter_refresh_sptep()
16 iter->old_spte = kvm_tdp_mmu_read_spte(iter->sptep); in tdp_iter_refresh_sptep()
25 iter->yielded = false; in tdp_iter_restart()
26 iter->yielded_gfn = iter->next_last_level_gfn; in tdp_iter_restart()
27 iter->level = iter->root_level; in tdp_iter_restart()
29 iter->gfn = gfn_round_for_level(iter->next_last_level_gfn, iter->level); in tdp_iter_restart()
32 iter->valid = true; in tdp_iter_restart()
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H A Dmmu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
52 #include <asm/page.h>
57 #include <asm/spec-ctrl.h>
64 int __read_mostly nx_huge_pages = -1;
100 * When setting this variable to true it enables Two-Dimensional-Paging
101 * where the hardware walks 2 page tables:
102 * 1. the guest-virtual to guest-physical
103 * 2. while doing 1. it walks guest-physical to host-physical
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H A Dtdp_mmu.c1 // SPDX-License-Identifier: GPL-2.0
17 INIT_LIST_HEAD(&kvm->arch.tdp_mmu_roots); in kvm_mmu_init_tdp_mmu()
18 spin_lock_init(&kvm->arch.tdp_mmu_pages_lock); in kvm_mmu_init_tdp_mmu()
26 lockdep_assert_held_read(&kvm->mmu_lock); in kvm_lockdep_assert_mmu_lock_held()
28 lockdep_assert_held_write(&kvm->mmu_lock); in kvm_lockdep_assert_mmu_lock_held()
43 WARN_ON(atomic64_read(&kvm->arch.tdp_mmu_pages)); in kvm_mmu_uninit_tdp_mmu()
44 WARN_ON(!list_empty(&kvm->arch.tdp_mmu_roots)); in kvm_mmu_uninit_tdp_mmu()
56 free_page((unsigned long)sp->spt); in tdp_mmu_free_sp()
61 * This is called through call_rcu in order to free TDP page table memory
64 * By only accessing TDP MMU page table memory in an RCU read critical
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/linux/fs/verity/
H A Dverify.c1 // SPDX-License-Identifier: GPL-2.0
3 * Data verification functions, i.e. hooks for ->readahead()
19 static bool is_hash_block_verified(struct fsverity_info *vi, struct page *hpage, in is_hash_block_verified()
26 * When the Merkle tree block size and page size are the same, then the in is_hash_block_verified()
27 * ->hash_block_verified bitmap isn't allocated, and we use PG_checked in is_hash_block_verified()
28 * to directly indicate whether the page's block has been verified. in is_hash_block_verified()
30 * Using PG_checked also guarantees that we re-verify hash pages that in is_hash_block_verified()
31 * get evicted and re-instantiated from the backing storage, as new in is_hash_block_verified()
34 if (!vi->hash_block_verified) in is_hash_block_verified()
38 * When the Merkle tree block size and page size differ, we use a bitmap in is_hash_block_verified()
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/linux/scripts/gdb/linux/
H A Dpgtable.py1 # SPDX-License-Identifier: GPL-2.0-only
5 # routines to introspect page table
18 def page_mask(level=1): argument
20 if level == 1:
23 elif level == 2:
26 elif level == 3:
29 raise Exception(f'Unknown page level: {level}')
44 return (bit_start, bit_end), data >> bit_start & ((1 << (1 + bit_end - bit_start)) - 1)
46 def entry_va(level, phys_addr, translating_va): argument
47 def start_bit(level): argument
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/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dcache.json78 …"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts …
84 …"PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event …
108 "PublicDescription": "Level 1 data cache late miss",
114 "PublicDescription": "Level 1 data cache prefetch request",
120 "PublicDescription": "Level 2 data cache prefetch request",
126 "PublicDescription": "Level 1 stage 2 TLB refill",
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
135 "BriefDescription": "Page walk, L0 stage-1 hit"
138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
141 "BriefDescription": "Page walk, L1 stage-1 hit"
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/linux/fs/f2fs/
H A Ddir.c1 // SPDX-License-Identifier: GPL-2.0
25 return ((unsigned long long) (i_size_read(inode) + PAGE_SIZE - 1)) in dir_blocks()
29 static unsigned int dir_buckets(unsigned int level, int dir_level) in dir_buckets() argument
31 if (level + dir_level < MAX_DIR_HASH_DEPTH / 2) in dir_buckets()
32 return BIT(level + dir_level); in dir_buckets()
37 static unsigned int bucket_blocks(unsigned int level) in bucket_blocks() argument
39 if (level < MAX_DIR_HASH_DEPTH / 2) in bucket_blocks()
46 /* If @dir is casefolded, initialize @fname->cf_name from @fname->usr_fname. */
50 struct super_block *sb = dir->i_sb; in f2fs_init_casefolded_name()
55 !is_dot_dotdot(fname->usr_fname->name, fname->usr_fname->len)) { in f2fs_init_casefolded_name()
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/linux/Documentation/virt/kvm/x86/
H A Dmmu.rst1 .. SPDX-License-Identifier: GPL-2.0
13 - correctness:
18 - security:
21 - performance:
23 - scaling:
25 - hardware:
27 - integration:
29 so that swapping, page migration, page merging, transparent
31 - dirty tracking:
33 and framebuffer-based displays
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vm_pt.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
31 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
37 unsigned int level; member
41 * amdgpu_vm_pt_level_shift - return the addr shift for each level
44 * @level: VMPT level
47 * The number of bits the pfn needs to be right shifted for a level.
50 unsigned int level) in amdgpu_vm_pt_level_shift() argument
52 switch (level) { in amdgpu_vm_pt_level_shift()
56 return 9 * (AMDGPU_VM_PDB0 - level) + in amdgpu_vm_pt_level_shift()
57 adev->vm_manager.block_size; in amdgpu_vm_pt_level_shift()
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/linux/arch/powerpc/include/asm/nohash/64/
H A Dpgtable-4k.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm-generic/pgtable-nop4d.h>
8 * Entries per page directory level. The PTE level must use a 64b record
9 * for each page table entry. The PMD and PGD level use a 32b record for
10 * each entry by assuming that each entry is page aligned.
29 /* PMD_SHIFT determines what a second-level page table entry can map */
32 #define PMD_MASK (~(PMD_SIZE-1))
34 /* PUD_SHIFT determines what a third-level page table entry can map */
37 #define PUD_MASK (~(PUD_SIZE-1))
39 /* PGDIR_SHIFT determines what a fourth-level page table entry can map */
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/linux/arch/arc/include/asm/
H A Dpgtable-levels.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * 2 level paging setup for software walked MMUv3 (ARC700) and MMUv4 (HS)
19 * -------------------------------------------------------
20 * | | <---------- PGDIR_SHIFT ----------> |
21 * | | | <-- PAGE_SHIFT --> |
22 * -------------------------------------------------------
24 * | | --> off in page frame
25 * | ---> index into Page Table
26 * ----> index into Page Directory
29 * However enabling of super page in a 2 level regime pegs PGDIR_SHIFT to
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/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Dvirtual-memory.json3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director…
11 …the number of first level TLB misses but second level hits due to a demand load that did not start…
19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
23 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
32 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
41 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
50 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
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/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A Dvirtual-memory.json3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director…
11 …the number of first level TLB misses but second level hits due to a demand load that did not start…
19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page…
23 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag…
32 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
41 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
50 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
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/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dmarked.json10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond …
20 … Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same …
45 …efDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 d…
50 …efDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 d…
60 …iption": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marke…
70 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa…
95 …Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the …
100 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa…
140 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc…
170 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d…
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/linux/arch/x86/mm/pat/
H A Dset_memory.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <asm/hyperv-tlfs.h>
41 * The current flushing context - we pass it instead of 5 arguments:
55 struct page **pages;
69 * entries change the page attribute in parallel to some other cpu
70 * splitting a large page entry along with changing the attribute.
87 void update_page_count(int level, unsigned long pages) in update_page_count() argument
91 direct_pages_count[level] += pages; in update_page_count()
95 static void split_page_count(int level) in split_page_count() argument
97 if (direct_pages_count[level] == 0) in split_page_count()
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/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Dvirtual-memory.json3 …the number of first level TLB misses but second level hits due to a demand load that did not start…
11 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.",
19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
23 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
32 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
37 …"BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch)…
41 …page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is o…
46 …iption": "Counts the number of first level TLB misses but second level hits due to stores that did…
54 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa…
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/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A Dvirtual-memory.json3 …the number of first level TLB misses but second level hits due to a demand load that did not start…
11 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.",
19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
23 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag…
32 …page walks completed due to loads (including SW prefetches) whose address translations missed in a…
37 …"BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch)…
41 …page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is o…
46 …iption": "Counts the number of first level TLB misses but second level hits due to stores that did…
54 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa…
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/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A Dvirtual-memory.json3 "BriefDescription": "Page walk for a large page completed for Demand load.",
11 … load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
15 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
20 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag…
24 … "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
29 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz…
33 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
38 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
47 "BriefDescription": "Store misses in all DTLB levels that cause page walks",
51 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).",
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/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A Dvirtual-memory.json3 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz…
11 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
19 "BriefDescription": "Page walk for a large page completed for Demand load.",
27 … load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.",
31 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand…
36 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag…
40 … "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.",
45 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz…
49 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema…
54 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.",
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/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A Dvirtual-memory.json3 …the number of first level TLB misses but second level hits due to a demand load that did not start…
16 …licDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
22 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
27 …ublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page wa…
33 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.",
42 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size…
46 …s completed page walks (all page sizes) caused by demand data loads. This implies it missed in th…
52 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
56 …leted page walks (1G sizes) caused by demand data loads. This implies address translations missed…
62 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or …
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/linux/arch/x86/boot/compressed/
H A Dpgtable_64.c1 // SPDX-License-Identifier: GPL-2.0
50 * Only look for values in the legacy ROM for non-EFI system. in find_trampoline_placement()
52 signature = (char *)&boot_params_ptr->efi_info.efi_loader_signature; in find_trampoline_placement()
68 for (i = boot_params_ptr->e820_entries - 1; i >= 0; i--) { in find_trampoline_placement()
71 entry = &boot_params_ptr->e820_table[i]; in find_trampoline_placement()
74 if (bios_start <= entry->addr) in find_trampoline_placement()
77 /* Skip non-RAM entries. */ in find_trampoline_placement()
78 if (entry->type != E820_TYPE_RAM) in find_trampoline_placement()
82 if (bios_start > entry->addr + entry->size) in find_trampoline_placement()
83 new = entry->addr + entry->size; in find_trampoline_placement()
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/linux/arch/hexagon/include/asm/
H A Dvm_mmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Hexagon VM page table entry definitions
5 * Copyright (c) 2010-2011,2013 The Linux Foundation. All rights reserved.
13 * page tables.
15 * Virtual machine MMU allows first-level entries to either be
16 * single-level lookup PTEs for very large pages, or PDEs pointing
17 * to second-level PTEs for smaller pages. If PTE is single-level,
19 * virtual memory subsystem information about the page, and that state
23 /* S or Page Size field in PDE */
34 /* Masks for L2 page table pointer, as function of page size */
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