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/linux/drivers/gpu/drm/xe/
H A D	xe_pt_walk.c	1 // SPDX-License-Identifier: GPL-2.0-only 8 * DOC: GPU page-table tree walking. 9 * The utilities in this file are similar to the CPU page-table walk 11 * the various levels of a page-table tree with an unsigned integer rather 12 * than by name. 0 is the lowest level, and page-tables with level 0 can 14 * can. The user of the utilities determines the highest level. 17 * Each struct xe_ptw, regardless of level is referred to as a page table, and 18 * multiple page tables typically form a page table tree with page tables at 19 * intermediate levels being page directories pointing at page tables at lower 20 * levels. A shared page table for a given address range is a page-table which [all …]
H A D	xe_pt_walk.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 12 struct xe_ptw - base class for driver pagetable subclassing. 16 * Drivers could subclass this, and if it's a page-directory, typically 25 * struct xe_pt_walk - Embeddable struct for walk parameters 31 * @shifts: Array of page-table entry shifts used for the 32 * different levels, starting out with the leaf level 0 33 * page-shift as the first entry. It's legal for this pointer to be 37 /** @max_level: Highest populated level in @sizes / 51 typedef xe_pt_entry_fn - gpu page-table-walk callback-function 52 * @parent: The parent page.table. [all …]
/linux/scripts/gdb/linux/
H A D	pgtable.py	`1 # SPDX-License-Identifier: GPL-2.0-only 5 # routines to introspect page table 18 def page_mask(level=1): argument 20 if level == 1: 23 elif level == 2: 26 elif level == 3: 29 raise Exception(f'Unknown page leve 46 entry_va(level, phys_addr, translating_va) global() argument 47 start_bit(level) global() argument 89 __init__(self, address, level) global() argument 154 page_size_line(ps_bit, ps, level) global() argument [all...]`
/linux/arch/arm64/include/asm/
H A D	kvm_pgtable.h	1 // SPDX-License-Identifier: GPL-2.0-only 14 #define KVM_PGTABLE_FIRST_LEVEL -1 18 * The largest supported block sizes for KVM (no 52-bit PA support): 19 * - 4K (level 1): 1GB 20 * - 16K (level 2): 32MB 21 * - 64K (level 2): 512MB 60 #define KVM_PHYS_INVALID (-1ULL) 104 * Used to indicate a pte for which a 'break-before-make' sequence is in 154 static inline u64 kvm_granule_shift(s8 level) in kvm_granule_shift() argument 157 return ARM64_HW_PGTABLE_LEVEL_SHIFT(level); in kvm_granule_shift() [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A D	cache.json	78 …"PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts … 84 …"PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event … 108 "PublicDescription": "Level 1 data cache late miss", 114 "PublicDescription": "Level 1 data cache prefetch request", 120 "PublicDescription": "Level 2 data cache prefetch request", 126 "PublicDescription": "Level 1 stage 2 TLB refill", 132 "PublicDescription": "Page walk cache level-0 stage-1 hit", 135 "BriefDescription": "Page walk, L0 stage-1 hit" 138 "PublicDescription": "Page walk cache level-1 stage-1 hit", 141 "BriefDescription": "Page walk, L1 stage-1 hit" [all …]
/linux/fs/verity/
H A D	verify.c	1 // SPDX-License-Identifier: GPL-2.0 3 * Data verification functions, i.e. hooks for ->readahead() 44 static bool is_hash_block_verified(struct fsverity_info vi, struct page hpage, in is_hash_block_verified() 51 * When the Merkle tree block size and page size are the same, then the in is_hash_block_verified() 52 * ->hash_block_verified bitmap isn't allocated, and we use PG_checked in is_hash_block_verified() 53 * to directly indicate whether the page's block has been verified. in is_hash_block_verified() 55 * Using PG_checked also guarantees that we re-verify hash pages that in is_hash_block_verified() 56 * get evicted and re-instantiated from the backing storage, as new in is_hash_block_verified() 59 if (!vi->hash_block_verified) in is_hash_block_verified() 63 * When the Merkle tree block size and page size differ, we use a bitmap in is_hash_block_verified() [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 11 …the number of first level TLB misses but second level hits due to a demand load that did not start… 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 23 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 32 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 41 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 50 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 11 …the number of first level TLB misses but second level hits due to a demand load that did not start… 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 23 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 32 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 41 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 50 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… [all …]
/linux/arch/x86/kvm/mmu/
H A D	paging_tmpl.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 3 Kernel-based Virtual Machine driver for Linux 5 * This module enables machines with Intel VT-x extensions to run virtual 19 * The MMU needs to be able to access/walk 32-bit and 64-bit guest page tables, 21 * once per guest PTE type. The per-type defines are #undef'd at the end. 50 (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT) 58 #define PT_HAVE_ACCESSED_DIRTY(mmu) (!(mmu)->cpu_role.base.ad_disabled) 64 /* Common logic, but per-type values. These also need to be undefined. / 77 The guest_walker structure emulates the behavior of the hardware page 81 int level; member [all …]
H A D	mmu_internal.h	1 /* SPDX-License-Identifier: GPL-2.0 / 17 / Page table builder macros common to shadow (host) PTEs and guest PTEs. / 19 #define __PT_LEVEL_SHIFT(level, bits_per_level) \ argument 20 (PAGE_SHIFT + ((level) - 1) (bits_per_level)) 21 #define __PT_INDEX(address, level, bits_per_level) \ argument 22 (((address) >> __PT_LEVEL_SHIFT(level, bits_per_level)) & ((1 << (bits_per_level)) - 1)) 24 #define __PT_LVL_ADDR_MASK(base_addr_mask, level, bits_per_level) \ argument 25 ((base_addr_mask) & ~((1ULL << (PAGE_SHIFT + (((level) - 1) * (bits_per_level)))) - 1)) 27 #define __PT_LVL_OFFSET_MASK(base_addr_mask, level, bits_per_level) \ argument 28 ((base_addr_mask) & ((1ULL << (PAGE_SHIFT + (((level) - 1) * (bits_per_level)))) - 1)) [all …]
H A D	tdp_mmu.c	1 // SPDX-License-Identifier: GPL-2.0 17 INIT_LIST_HEAD(&kvm->arch.tdp_mmu_roots); in kvm_mmu_init_tdp_mmu() 18 spin_lock_init(&kvm->arch.tdp_mmu_pages_lock); in kvm_mmu_init_tdp_mmu() 26 lockdep_assert_held_read(&kvm->mmu_lock); in kvm_lockdep_assert_mmu_lock_held() 28 lockdep_assert_held_write(&kvm->mmu_lock); in kvm_lockdep_assert_mmu_lock_held() 44 KVM_MMU_WARN_ON(atomic64_read(&kvm->arch.tdp_mmu_pages)); in kvm_mmu_uninit_tdp_mmu() 46 WARN_ON(!list_empty(&kvm->arch.tdp_mmu_roots)); in kvm_mmu_uninit_tdp_mmu() 58 free_page((unsigned long)sp->external_spt); in tdp_mmu_free_sp() 59 free_page((unsigned long)sp->spt); in tdp_mmu_free_sp() 64 * This is called through call_rcu in order to free TDP page table memory [all …]
H A D	mmu.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Kernel-based Virtual Machine driver for Linux 5 * This module enables machines with Intel VT-x extensions to run virtual 52 #include <asm/page.h> 57 #include <asm/spec-ctrl.h> 64 int __read_mostly nx_huge_pages = -1; 100 * When setting this variable to true it enables Two-Dimensional-Paging 101 * where the hardware walks 2 page tables: 102 * 1. the guest-virtual to guest-physical 103 * 2. while doing 1. it walks guest-physical to host-physical [all …]
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A D	virtual-memory.json	3 …efDescription": "Counts the number of page walks initiated by a demand load that missed the first … 12 …the number of first level TLB misses but second level hits due to a demand load that did not start… 25 …licDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).", 31 … "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.", 36 …ublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page wa… 42 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 46 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 52 …"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page size… 56 …s completed page walks (all page sizes) caused by demand data loads. This implies it missed in th… 62 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.", [all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A D	amdgpu_vm_pt.c	1 // SPDX-License-Identifier: GPL-2.0 OR MIT 32 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt 38 unsigned int level; member 42 * amdgpu_vm_pt_level_shift - return the addr shift for each level 45 * @level: VMPT level 48 * The number of bits the pfn needs to be right shifted for a level. 51 unsigned int level) in amdgpu_vm_pt_level_shift() argument 53 switch (level) { in amdgpu_vm_pt_level_shift() 57 return 9 * (AMDGPU_VM_PDB0 - level) + in amdgpu_vm_pt_level_shift() 58 adev->vm_manager.block_size; in amdgpu_vm_pt_level_shift() [all …]
/linux/drivers/iommu/amd/
H A D	io_pgtable_v2.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * CPU-agnostic AMD IO page table v2 allocator. 10 #define pr_fmt(fmt) "AMD-Vi: " fmt 14 #include <linux/io-pgtable.h> 21 #include "../iommu-pages.h" 26 #define IOMMU_PAGE_PWT BIT_ULL(3) /* Page write through / 27 #define IOMMU_PAGE_PCD BIT_ULL(4) / Page cache disabled / 30 #define IOMMU_PAGE_PSE BIT_ULL(7) / Page Size Extensions / 49 static inline u64 set_pgtable_attr(u64 page) in set_pgtable_attr() argument 56 return (iommu_virt_to_phys(page) \| prot); in set_pgtable_attr() [all …]
/linux/Documentation/virt/kvm/x86/
H A D	mmu.rst	`1 .. SPDX-License-Identifier: GPL-2.0 13 - correctness: 18 - security: 21 - performance: 23 - scaling: 25 - hardware: 27 - integration: 29 so that swapping, page migration, page merging, transparent 31 - dirty tracking: 33 and framebuffer-based displays [all …]`
/linux/arch/powerpc/include/asm/nohash/64/
H A D	pgtable-4k.h	1 /* SPDX-License-Identifier: GPL-2.0 / 5 #include <asm-generic/pgtable-nop4d.h> 8 Entries per page directory level. The PTE level must use a 64b record 9 * for each page table entry. The PMD and PGD level use a 32b record for 10 * each entry by assuming that each entry is page aligned. 29 /* PMD_SHIFT determines what a second-level page table entry can map / 32 #define PMD_MASK (~(PMD_SIZE-1)) 34 / PUD_SHIFT determines what a third-level page table entry can map / 37 #define PUD_MASK (~(PUD_SIZE-1)) 39 / PGDIR_SHIFT determines what a fourth-level page table entry can map */ [all …]
/linux/arch/x86/mm/pat/
H A D	set_memory.c	1 // SPDX-License-Identifier: GPL-2.0-only 39 * The current flushing context - we pass it instead of 5 arguments: 53 struct page *pages; 67 entries change the page attribute in parallel to some other cpu 68 * splitting a large page entry along with changing the attribute. 86 void update_page_count(int level, unsigned long pages) in update_page_count() argument 90 direct_pages_count[level] += pages; in update_page_count() 94 static void split_page_count(int level) in split_page_count() argument 96 if (direct_pages_count[level] == 0) in split_page_count() 99 direct_pages_count[level]--; in split_page_count() [all …]
/linux/arch/x86/mm/
H A D	mem_encrypt_amd.c	1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2016-2024 Advanced Micro Devices, Inc. 13 #include <linux/dma-direct.h> 19 #include <linux/dma-mapping.h> 29 #include <asm/processor-flags.h> 49 /* Buffer used for early in-place encryption by BSP, no locking needed / 53 SNP-specific routine which needs to additionally change the page state from 64 * @paddr needs to be accessed decrypted, mark the page shared in in snp_memcpy() 71 /* Restore the page state after the memcpy. / in snp_memcpy() 75 @paddr need to be accessed encrypted, no need for the page state in snp_memcpy() [all …]
/linux/tools/testing/selftests/kvm/lib/loongarch/
H A D	processor.c	1 // SPDX-License-Identifier: GPL-2.0 15 static uint64_t virt_pte_index(struct kvm_vm vm, vm_vaddr_t gva, int level) in virt_pte_index() argument 20 shift = level (vm->page_shift - 3) + vm->page_shift; in virt_pte_index() 21 mask = (1UL << (vm->page_shift - 3)) - 1; in virt_pte_index() 27 return entry & ~((0x1UL << vm->page_shift) - 1); in pte_addr() 32 return 1 << (vm->page_shift - 3); in ptrs_per_pte() 41 ptrs_per_pte = 1 << (vm->page_shift - 3); in virt_set_pgtable() 51 if (vm->pgd_created) in virt_arch_pgd_alloc() 55 for (i = 0; i < vm->pgtable_levels; i++) { in virt_arch_pgd_alloc() 58 vm->memslots[MEM_REGION_PT]); in virt_arch_pgd_alloc() [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	marked.json	10 …"BriefDescription": "A Page Directory Entry was reloaded to a level 1 page walk cache from beyond … 20 … Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same … 45 …efDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L2 d… 50 …efDescription": "A Page Table Entry was reloaded to a level 3 page walk cache from the core's L3 d… 60 …iption": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marke… 70 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa… 95 …Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the … 100 …Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the sa… 140 …"BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the loc… 170 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without d… [all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	virtual-memory.json	3 …the number of first level TLB misses but second level hits due to a demand load that did not start… 11 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.", 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 23 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 32 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 37 …"BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch)… 41 …page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is o… 46 …iption": "Counts the number of first level TLB misses but second level hits due to stores that did… 54 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa… [all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	virtual-memory.json	3 …the number of first level TLB misses but second level hits due to a demand load that did not start… 11 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.", 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 23 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 32 …page walks completed due to loads (including SW prefetches) whose address translations missed in a… 37 …"BriefDescription": "Counts the number of page walks outstanding for Loads (demand or SW prefetch)… 41 …page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is o… 46 …iption": "Counts the number of first level TLB misses but second level hits due to stores that did… 54 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa… [all …]
/linux/tools/perf/pmu-events/arch/x86/ivybridge/
H A D	virtual-memory.json	3 "BriefDescription": "Page walk for a large page completed for Demand load.", 11 … load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", 15 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand… 20 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag… 24 … "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", 29 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz… 33 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema… 38 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", 47 "BriefDescription": "Store misses in all DTLB levels that cause page walks", 51 … "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", [all …]
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	virtual-memory.json	3 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz… 11 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", 19 "BriefDescription": "Page walk for a large page completed for Demand load.", 27 … load Miss in all translation lookaside buffer (TLB) levels causes an page walk of any page size.", 31 …"PublicDescription": "Misses in all TLB levels that cause a page walk of any page size from demand… 36 …cription": "Load operations that miss the first DTLB level but hit the second and do not cause pag… 40 … "PublicDescription": "Counts load operations that missed 1st level DTLB but hit the 2nd level.", 45 …in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page siz… 49 …"PublicDescription": "Misses in all TLB levels that caused page walk completed of any size by dema… 54 "BriefDescription": "Demand load cycles page miss handler (PMH) is busy with this walk.", [all …]

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