Searched +full:p5020 +full:- +full:clockgen (Results 1 – 5 of 5) sorted by relevance
/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | fsl,qoriq-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <Frank.Li@nxp.com> 24 --------------- ------------- 25 1.0 p4080, p5020, p5040 30 The clockgen node should act as a clock provider, though in older device 31 trees the children of the clockgen node are the clock providers. 36 - items: [all …]
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H A D | qoriq-clock.txt | 14 --------------- ------------- 15 1.0 p4080, p5020, p5040 21 - compatible: Should contain a chip-specific clock block compatible 22 string and (if applicable) may contain a chassis-version clock 25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as: 26 * "fsl,p2041-clockgen" 27 * "fsl,p3041-clockgen" 28 * "fsl,p4080-clockgen" 29 * "fsl,p5020-clockgen" 30 * "fsl,p5040-clockgen" [all …]
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
H A D | p5020si-pre.dtsi | 2 * P5020/P5010 Silicon/SoC Device Tree Source (pre include) 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc. 35 /dts-v1/; 40 compatible = "fsl,P5020"; 41 #address-cells = <2>; 42 #size-cells = <2>; 43 interrupt-parent = <&mpic>; 93 #address-cells = <1>; 94 #size-cells = <0>; 99 clocks = <&clockgen 1 0>; [all …]
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H A D | p5020si-post.dtsi | 2 * P5020/5010 Silicon/SoC Device Tree Source (post include) 4 * Copyright 2011 - 2015 Freescale Semiconductor Inc. 36 compatible = "fsl,bman-fbpr"; 37 alloc-ranges = <0 0 0x10000 0>; 41 compatible = "fsl,qman-fqd"; 42 alloc-ranges = <0 0 0x10000 0>; 46 compatible = "fsl,qman-pfdr"; 47 alloc-ranges = <0 0 0x10000 0>; 51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus"; 53 #address-cells = <2>; [all …]
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/freebsd/sys/dts/powerpc/ |
H A D | p5020si.dtsi | 2 * P5020 Silicon Device Tree Source 4 * Copyright 2010-2011 Freescale Semiconductor Inc. 35 /dts-v1/; 38 compatible = "fsl,P5020"; 39 #address-cells = <2>; 40 #size-cells = <2>; 41 interrupt-parent = <&mpic>; 108 #address-cells = <1>; 109 #size-cells = <0>; 114 bus-frequency = <799999998>; [all …]
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